Path: ...!eternal-september.org!feeder3.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail
From: Stephen Fuld <sfuld@alumni.cmu.edu.invalid>
Newsgroups: comp.arch
Subject: Re: Tonights Tradeoff
Date: Wed, 11 Sep 2024 08:48:03 -0700
Organization: A noiseless patient Spider
Lines: 28
Message-ID: <vbse3j$f01n$2@dont-email.me>
References: <vbgdms$152jq$1@dont-email.me>
 <17537125c53e616e22f772e5bcd61943@www.novabbs.org>
 <vbj5af$1puhu$1@dont-email.me>
 <a37e9bd652d7674493750ccc04674759@www.novabbs.org>
 <vbog6d$2p2rc$1@dont-email.me> <vboqpp$2r5v4$1@dont-email.me>
 <vbpmqr$30vto$1@dont-email.me> <vbqcds$35l1q$2@dont-email.me>
 <vbs7ff$3koub$1@dont-email.me>
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8; format=flowed
Content-Transfer-Encoding: 7bit
Injection-Date: Wed, 11 Sep 2024 17:48:03 +0200 (CEST)
Injection-Info: dont-email.me; posting-host="6a662a8a00c851f8c26756079048eecd";
	logging-data="491575"; mail-complaints-to="abuse@eternal-september.org";	posting-account="U2FsdGVkX1+QPvtiAVDrukkNwoSQFahxNmj47xr103E="
User-Agent: Mozilla Thunderbird
Cancel-Lock: sha1:0IV8T15faHK9Yzm0NEpBRl1qZAM=
In-Reply-To: <vbs7ff$3koub$1@dont-email.me>
Content-Language: en-US
Bytes: 2130

On 9/11/2024 6:54 AM, Robert Finch wrote:

snip


> I have found that there can be a lot of registers available if they are 
> implemented in BRAMs. BRAMs have lots of depth compared to LUT RAMs. 
> BRAMs have a one cycle latency but that is just part of the pipeline. In 
> Q+ about 40k LUTs are being used just to keep track of registers. 
> (rename mappings and checkpoints).
> 
> Given a lot of available registers I keep considering trying a VLIW 
> design similar to the Itanium, rotating register and all. But I have a 
> lot invested in OoO.
> 
> 
> Q+ has seven in-order pipeline stages before things get to the re-order 
> buffer. 

Does each of these take a clock cycle?  If so, that seems excessive. 
What is your cost for a mis-predicted branch?




-- 
  - Stephen Fuld
(e-mail address disguised to prevent spam)