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From: Lasse Langwadt <llc@fonz.dk>
Newsgroups: sci.electronics.design,comp.arch.fpga,comp.sys.raspberry.pi
Subject: Re: configuring an Efinix T20
Date: Thu, 12 Sep 2024 00:44:35 +0200
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On 9/7/24 00:50, john larkin wrote:
> 
> I'm planning to use a Raspberry Pi RP2040 processor chip to configure
> and then talk to an Efinix T20-FG256 FPGA.
> 
> Has anyone done this, or at least configured a T20 from a
> microprocessor?
> 
> The RP2040 only has 30 GPIO pins, and many are dedicated to other
> stuff, so we want to share a lot of things on one giant SPI bus,
> including the FPGA config and then an SPI port on the FPGA to read and
> write registers.
> 
> It looks like four of the T20 config pins need pullups. I wonder why
> their guidelines show four separate resistors. Why not one resistor?
> Why have resistors at all?
> 
> SS_N needs a pulldown. Why not ground it?
> 

seems like you don't need resistors, 
https://www.efinixinc.com/docs/an006-configuring-trion-fpgas-v6.1.pdf 
pages 10

"Set CBUS2, CBUS1, CBUS0, SS_N, and TEST_N using a pull-up or pull-down 
resistor, or
drive them with an external active device."

and in some packages, page 8

"Important: The CCK pin in Q100F3 packages are only
available in user mode when the LVDS TX resources are
not in use. The CCK pin should not be toggled when any
LVDS TX is used."


> https://www.dropbox.com/scl/fi/x0gvvwqg42vhryu6610ve/Efinix_Config_1.jpg?rlkey=udy24brtumvdzfd2sp4l6yhwf&raw=1
> 
> 
> It's always a moment to celebrate when a "config done" LED lights up.
> 
> I could easily get this wrong, so it would be great if I posted some
> schematics and notes and someone could eyeball them for me.