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From: Robert Finch <robfi680@gmail.com>
Newsgroups: comp.arch
Subject: Re: Tonights Tradeoff
Date: Wed, 11 Sep 2024 23:37:22 -0400
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On 2024-09-11 11:48 a.m., Stephen Fuld wrote:
> On 9/11/2024 6:54 AM, Robert Finch wrote:
> 
> snip
> 
> 
>> I have found that there can be a lot of registers available if they 
>> are implemented in BRAMs. BRAMs have lots of depth compared to LUT 
>> RAMs. BRAMs have a one cycle latency but that is just part of the 
>> pipeline. In Q+ about 40k LUTs are being used just to keep track of 
>> registers. (rename mappings and checkpoints).
>>
>> Given a lot of available registers I keep considering trying a VLIW 
>> design similar to the Itanium, rotating register and all. But I have a 
>> lot invested in OoO.
>>
>>
>> Q+ has seven in-order pipeline stages before things get to the re- 
>> order buffer. 
> 
> Does each of these take a clock cycle?  If so, that seems excessive. 
> What is your cost for a mis-predicted branch?
> 
> 
> 
> 
Each stage takes one clock cycle. Unconditional branches are detected at 
the second stage and taken then so they do not consume as many clocks. 
There are two extra stages to handle vector instructions. Those two 
stages could be removed if vectors are not needed.

Mis-predicted branches are really expensive. They take about six clocks, 
plus the seven clocks to refill the pipeline, so it is about 13 clocks. 
Seems like it should be possible to reduce the number of clocks of 
processing during the miss, but I have not got around to it yet. There 
is a branch miss state machine that restores the checkpoint. Branches 
need a lot of work yet.

I am not sure how well the branch prediction works. Instruction runs in 
SIM are not long enough yet. Something in the AGEN/TLB/LSQ is not 
working correctly yet, leading to bad memory cycles.