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From: David Brown <david.brown@hesbynett.no>
Newsgroups: comp.arch
Subject: Re: Computer architects leaving Intel...
Date: Mon, 16 Sep 2024 20:11:20 +0200
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On 16/09/2024 19:51, MitchAlsup1 wrote:
> On Mon, 16 Sep 2024 8:34:19 +0000, David Brown wrote:
> 
>> On 15/09/2024 21:13, MitchAlsup1 wrote:
>>>
>>> As to HW sadism:: this not not <realistically> any harder than mis-
>>> aligned DW accesses from the cache. Many ISA from the rather distant
>>> past could do these rather efficiently {360 SRDL,...}
>>>
>>
>> Anyone who designs a data structure with a bit-field that spans two
>> 64-bit parts of a struct is probably ignorant of C bit-fields and
>> software in general.  It is highly unlikely to be necessary or even
>> beneficial from the hardware viewpoint, but really inconvenient on the
>> software side (whether you use bit-fields or not).
> 
> Sometimes you don't have a choice::
> x86-64 segment registers.
> PCIe MMI/O registers,
> ..

The folks designing those register setups had a choice, and made a bad 
choice from the viewpoint of software (whether it be C, assembly, or any 
other language).

It's conceivable that it was the right choice on balance, considering 
many factors.  And it's certainly more believable that it was an 
appropriate choice when sizes were smaller.  It is less believable that 
there is an overwhelming need to cross a 64-bit boundary.