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From: Waldek Hebisch <antispam@fricas.org>
Newsgroups: comp.arch
Subject: Re: Computer architects leaving Intel...
Date: Tue, 17 Sep 2024 01:36:46 -0000 (UTC)
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David Brown <david.brown@hesbynett.no> wrote:
> On 16/09/2024 19:51, MitchAlsup1 wrote:
>> On Mon, 16 Sep 2024 8:34:19 +0000, David Brown wrote:
>> 
>>> On 15/09/2024 21:13, MitchAlsup1 wrote:
>>>>
>>>> As to HW sadism:: this not not <realistically> any harder than mis-
>>>> aligned DW accesses from the cache. Many ISA from the rather distant
>>>> past could do these rather efficiently {360 SRDL,...}
>>>>
>>>
>>> Anyone who designs a data structure with a bit-field that spans two
>>> 64-bit parts of a struct is probably ignorant of C bit-fields and
>>> software in general.  It is highly unlikely to be necessary or even
>>> beneficial from the hardware viewpoint, but really inconvenient on the
>>> software side (whether you use bit-fields or not).
>> 
>> Sometimes you don't have a choice::
>> x86-64 segment registers.
>> PCIe MMI/O registers,
>> ..
> 
> The folks designing those register setups had a choice, and made a bad 
> choice from the viewpoint of software (whether it be C, assembly, or any 
> other language).
> 
> It's conceivable that it was the right choice on balance, considering 
> many factors.  And it's certainly more believable that it was an 
> appropriate choice when sizes were smaller.  It is less believable that 
> there is an overwhelming need to cross a 64-bit boundary.

Several pieces of software discoverd that "bad" smaller data
structures lead to faster execution.  Simply, smaller data structures
lead to better utilization of caches and busses, and efect due to
this was larger than cost of extra instructions.  So need to cross
64-bit boundary may be rare, but there will be cases when it is best
choice. 

-- 
                              Waldek Hebisch