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From: Bill Sloman <bill.sloman@ieee.org>
Newsgroups: sci.electronics.design
Subject: Re: DRAM accommodations
Date: Wed, 18 Sep 2024 00:04:09 +1000
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On 17/09/2024 11:47 pm, Chris Jones wrote:
> On 6/09/2024 8:54 am, Don Y wrote:
>> Given the high rate of memory errors in DRAM, what steps
>> are folks taking to mitigate the effects of these?
>>
>> Or, is ignorance truly bliss?  <frown>
>>
> 
> Do we know whether DRAM chips implement ECC internally? It seems an 
> obvious thing for them to do. Of course it wouldn't help with bad solder 
> joints on the DIMM, but it would help with many kinds of faults on the 
> chip.

It seems unlikely. The only ECC coding that I got close enough to  plan 
to implement used a 72-bit word to protect 64-bits of the word content.

I suppose there might be serial access DRAM chips that would spit out 
64-bit words, and they could offer ECC protection inside the chip by 
adding the 8-bit checksum when the data went in, and using it to correct 
the output whenever the data was read out.

-- 
Bill Sloman, Sydney