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From: piglet <erichpwagner@hotmail.com>
Newsgroups: sci.electronics.design
Subject: Re: faster DDS clock
Date: Wed, 18 Sep 2024 21:58:13 -0000 (UTC)
Organization: A noiseless patient Spider
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john larkin <jl@650pot.com> wrote:
> Assume a DAC being driven with an n-bit sine waveform at some clock
> frequency, and then a lowpass filter and a comparator, generating a
> programmable frequency clock.
> 
> Why not use both edges of the comparator output as our clock? That
> de-stresses everything by 2:1, which could well be a net win on jitter
> and such. Or gives twice the clock frequency with the same parts.
> 
> 

How important is it that the duty cycle is 50%? 

-- 
piglet