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From: Lawrence D'Oliveiro <ldo@nz.invalid>
Newsgroups: comp.arch
Subject: Re: Is Intel exceptionally unsuccessful as an architecture designer?
Date: Thu, 19 Sep 2024 23:37:00 -0000 (UTC)
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On Thu, 19 Sep 2024 16:09:15 +0000, MitchAlsup1 wrote:

> 400 cycles IS negligible.
> 400 cycles for each LD is non-negligible.
> 
> Remember LDs are 20%-22% of the instruction stream and with 400 cycles
> per LD you see an average of 80-cycles per instruction even if all other
> instructions take 1 cycle. This is 160× SLOWER than current CPUs. But
> GPUs with thousands of cores can use memory that slow and still deliver
> big gains in performance (6×-50×).

How can they do that? What proportion of their instruction stream is LDs? 
It seems to me they are accessing memory in 100% of their instructions, 
since they would have less sophisticated memory controllers than CPUs 
commonly have.