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From: Brett <ggtgp@yahoo.com>
Newsgroups: comp.arch
Subject: Re: Computer architects leaving Intel...
Date: Fri, 20 Sep 2024 00:12:48 -0000 (UTC)
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Injection-Info: dont-email.me; posting-host="a85e4f9367d946554eaf5f27f30799fd";
	logging-data="827368"; mail-complaints-to="abuse@eternal-september.org";	posting-account="U2FsdGVkX1+tzrDadRcc2ub+rQ72euiv"
User-Agent: NewsTap/5.5 (iPad)
Cancel-Lock: sha1:CExCC76NcNPtmEBQgLofA0yjUX4=
	sha1:cfUijsOXxBqQueG8mBXaWKSDTOA=
Bytes: 4481

MitchAlsup1 <mitchalsup@aol.com> wrote:
> On Thu, 19 Sep 2024 19:12:41 +0000, Brett wrote:
> 
>> MitchAlsup1 <mitchalsup@aol.com> wrote:
>>> On Thu, 19 Sep 2024 15:07:11 +0000, EricP wrote:
>> 
>> 
>>>> - register specifier fields are either source or dest, never both
>>> 
>>> I happen to be wishywashy on this
>> 
>> 
>> This is deeply interesting, can you expound on why it is fine a register
>> field can be shared by loads and stores, and sometimes both like x86.
> 
> My 66000 encodes store data register in the same field position as it
> encodes "what kind of branch" is being performed, and the same position
> as all calculation (and load) results.
> 
> I started doing this in 1982 with Mc88100 ISA, and never found a problem
> with the encoding nor in the decoding nor with the pipelining of it.
> 
> Let me be clear, I do not support necessarily damaging a source operand
> to fit in another destination as::
> 
>     ADD     SP,SP,#0x40
> 
> by specifying SP only once in the instruction.
> 
> So,
> 
>     +------+-----+-----+----------------+
>     | major| Rd  | Rs1 | whatever       |
>     +------+-----+-----+----------------+
>     |  BC  | cnd | Rs1 | label  offset  |
>     +------+-----+-----+----------------+
>     |  LD  | Rd  | Rb  | displacement   |
>     +------+-----+-----+----------------+
>     | ST   | Rs0 | Rb  | displacement   |
>     +------+-----+-----+----------------+
> 
> Is:
> a) no burden in encoding
> b) no burden in decoding
> c) no burden in pipelining
> d) no burden in stealing the Store data port late in the pipeline
>   {in particular, this saves lots of flip-flops deferring store
>    data until after cache hit, TLB hit, and data has arrived at
>    cache.}
> 
> I disagree with things like::
> 
>     +------+-----+-----+----------------+
>     | big OpCode | Rds | whatever       |
>     +------+-----+-----+----------------+
> 
> Where Rds means the specifier is used as both a source and destination.
> 
> Notice in my encoding one can ALWAYS take the register specification
> fields and wire them directly into the RF/renamer decoder ports.
> You lose this property the other way around.
> 
>> Classic RISC says the loads are critical, but no one is one wide today,
> 
> SiFive disagrees with you.
> 
>> so
>> stores matter for deconfliction…. And does stuff just fall out right to
>> allow both?
> 
> Can you restate what you wanted to say using different words or perhaps
> give an example ??
> 

A series of adds to the same register in a four wide design.

A = A + 1
A = A + B
A = A + C
A = A + D