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Path: ...!weretis.net!feeder8.news.weretis.net!eternal-september.org!feeder3.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: Brett <ggtgp@yahoo.com> Newsgroups: comp.arch Subject: Re: Computer architects leaving Intel... Date: Fri, 20 Sep 2024 00:12:48 -0000 (UTC) Organization: A noiseless patient Spider Lines: 81 Message-ID: <vciem0$p7v8$1@dont-email.me> References: <vaqgtl$3526$1@dont-email.me> <2024Sep11.123824@mips.complang.tuwien.ac.at> <vbsoro$3ol1a$1@dont-email.me> <867cbhgozo.fsf@linuxsc.com> <20240912142948.00002757@yahoo.com> <vbuu5n$9tue$1@dont-email.me> <20240915001153.000029bf@yahoo.com> <vc6jbk$5v9f$1@paganini.bofh.team> <20240915154038.0000016e@yahoo.com> <vc70sl$285g2$4@dont-email.me> <vc73bl$28v0v$1@dont-email.me> <OvEFO.70694$EEm7.38286@fx16.iad> <32a15246310ea544570564a6ea100cab@www.novabbs.org> <vc7a6h$2afrl$2@dont-email.me> <50cd3ba7c0cbb587a55dd67ae46fc9ce@www.novabbs.org> <vc8qic$2od19$1@dont-email.me> <fCXFO.4617$9Rk4.4393@fx37.iad> <vcb730$3ci7o$1@dont-email.me> <7cBGO.169512$_o_3.43954@fx17.iad> <vcffub$77jk$1@dont-email.me> <n7XGO.89096$15a6.87061@fx12.iad> <35b8ff2e6baa54c7aa22ec4edf45c3f9@www.novabbs.org> <vcht39$mbru$1@dont-email.me> <790b8efbbbb95a6e56ea52bc004f466a@www.novabbs.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Injection-Date: Fri, 20 Sep 2024 02:12:48 +0200 (CEST) Injection-Info: dont-email.me; posting-host="a85e4f9367d946554eaf5f27f30799fd"; logging-data="827368"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+tzrDadRcc2ub+rQ72euiv" User-Agent: NewsTap/5.5 (iPad) Cancel-Lock: sha1:CExCC76NcNPtmEBQgLofA0yjUX4= sha1:cfUijsOXxBqQueG8mBXaWKSDTOA= Bytes: 4481 MitchAlsup1 <mitchalsup@aol.com> wrote: > On Thu, 19 Sep 2024 19:12:41 +0000, Brett wrote: > >> MitchAlsup1 <mitchalsup@aol.com> wrote: >>> On Thu, 19 Sep 2024 15:07:11 +0000, EricP wrote: >> >> >>>> - register specifier fields are either source or dest, never both >>> >>> I happen to be wishywashy on this >> >> >> This is deeply interesting, can you expound on why it is fine a register >> field can be shared by loads and stores, and sometimes both like x86. > > My 66000 encodes store data register in the same field position as it > encodes "what kind of branch" is being performed, and the same position > as all calculation (and load) results. > > I started doing this in 1982 with Mc88100 ISA, and never found a problem > with the encoding nor in the decoding nor with the pipelining of it. > > Let me be clear, I do not support necessarily damaging a source operand > to fit in another destination as:: > > ADD SP,SP,#0x40 > > by specifying SP only once in the instruction. > > So, > > +------+-----+-----+----------------+ > | major| Rd | Rs1 | whatever | > +------+-----+-----+----------------+ > | BC | cnd | Rs1 | label offset | > +------+-----+-----+----------------+ > | LD | Rd | Rb | displacement | > +------+-----+-----+----------------+ > | ST | Rs0 | Rb | displacement | > +------+-----+-----+----------------+ > > Is: > a) no burden in encoding > b) no burden in decoding > c) no burden in pipelining > d) no burden in stealing the Store data port late in the pipeline > {in particular, this saves lots of flip-flops deferring store > data until after cache hit, TLB hit, and data has arrived at > cache.} > > I disagree with things like:: > > +------+-----+-----+----------------+ > | big OpCode | Rds | whatever | > +------+-----+-----+----------------+ > > Where Rds means the specifier is used as both a source and destination. > > Notice in my encoding one can ALWAYS take the register specification > fields and wire them directly into the RF/renamer decoder ports. > You lose this property the other way around. > >> Classic RISC says the loads are critical, but no one is one wide today, > > SiFive disagrees with you. > >> so >> stores matter for deconfliction…. And does stuff just fall out right to >> allow both? > > Can you restate what you wanted to say using different words or perhaps > give an example ?? > A series of adds to the same register in a four wide design. A = A + 1 A = A + B A = A + C A = A + D