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From: Lasse Langwadt <llc@fonz.dk>
Newsgroups: sci.electronics.design
Subject: Re: faster DDS clock
Date: Sun, 22 Sep 2024 18:37:54 +0200
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On 9/22/24 03:40, john larkin wrote:
> On Sat, 21 Sep 2024 18:37:26 -0700, john larkin <JL@gct.com> wrote:
> 
>> On Sun, 22 Sep 2024 03:11:53 +0200, Lasse Langwadt <llc@fonz.dk>
>> wrote:
>>
>>> On 9/21/24 17:42, john larkin wrote:
>>>> On Fri, 20 Sep 2024 00:30:28 +0200, Lasse Langwadt <llc@fonz.dk>
>>>> wrote:
>>>>
>>>>> On 9/19/24 05:57, john larkin wrote:
>>>>>> On Thu, 19 Sep 2024 03:28:09 -0000 (UTC), Phil Hobbs
>>>>>> <pcdhSpamMeSenseless@electrooptical.net> wrote:
>>>>>>
>>>>>>> john larkin <JL@gct.com> wrote:
>>>>>>>> On Wed, 18 Sep 2024 21:56:59 -0000 (UTC), Phil Hobbs
>>>>>>>> <pcdhSpamMeSenseless@electrooptical.net> wrote:
>>>>>>>>
>>>>>>>>> john larkin <jl@650pot.com> wrote:
>>>>>>>>>> Assume a DAC being driven with an n-bit sine waveform at some clock
>>>>>>>>>> frequency, and then a lowpass filter and a comparator, generating a
>>>>>>>>>> programmable frequency clock.
>>>>>>>>>>
>>>>>>>>>> Why not use both edges of the comparator output as our clock? That
>>>>>>>>>> de-stresses everything by 2:1, which could well be a net win on jitter
>>>>>>>>>> and such. Or gives twice the clock frequency with the same parts.
>>>>>>>>>>
>>>>>>>>>>
>>>>>>>>>
>>>>>>>>> The usual trouble is that you have to get the other edge from somewhere. An
>>>>>>>>> xor gate and an RC is typical.
>>>>>>>>>
>>>>>>>>> Any asymmetry in the square wave turns into subharmonic jitter.
>>>>>>>>>
>>>>>>>>> A 2:1 PLL would probably get my vote.
>>>>>>>
>>>>>>>>
>>>>>>>> I'm trying to make things cheaper and simpler. I need a clock that's
>>>>>>>> programmable up to maybe 20 or 25 MHz, and it would be nice to use
>>>>>>>> some relatively cheap dual DACs.
>>>>>>>
>>>>>>> Understood.  A Joergesque solution would be to use a discrete FET as part
>>>>>>> of the RC + XOR, and dork the ON resistance to square up the duty cycle.
>>>>>>> (He’d probably use a CD4007 DIY gate package to do a few at once. Maybe
>>>>>>> it’s possible to use a TinyLogic inverter with VDD open.)
>>>>>>>
>>>>>>> Cheers
>>>>>>>
>>>>>>> Phil Hobbs
>>>>>>
>>>>>> An LVDS line receiver would make a pretty good comparator, after the
>>>>>> filter.
>>>>>>
>>>>>> If I have enough balls (no pun intended) I can use an LVDS input of my
>>>>>> FPGA. One could even servo that to exactly 50%.
>>>>>>
>>>>>> I don't know if this FPGA could internally clock on both edges.
>>>>>>
>>>>>> But I can get a TI DAC908 for under $5, so may just clock that fast,
>>>>>> brute force at 100 MHz or so. That would make 20 MHz with a dinky
>>>>>> filter.
>>>>>>
>>>>>
>>>>> this will give you 3x10bit@140MHZ DACs for about the same price
>>>>> https://www.lcsc.com/product-detail/Digital-to-Analog-Converters-DAC_Analog-Devices-ADV7123KSTZ140-RL_C172724.html
>>>>>
>>>>> or 3x8bit@330MHz
>>>>> https://www.lcsc.com/product-detail/Digital-to-Analog-Converters-DAC_Analog-Devices-ADV7125JSTZ330_C662165.html
>>>>>
>>>>> if you opt for the Chinese clone, less than half for 3x10bit@240MHz
>>>>> https://www.lcsc.com/product-detail/Digital-to-Analog-Converters-DAC_HTCSEMI-HT7123ARQZ_C2886392.html
>>>>>
>>>>>
>>>>>
>>>>>
>>>>>
>>>>
>>>> It occurrs to me that the use for a 3-channel fast 10-bit DAC is to
>>>> drive a color CRT monitor, which I expect nobody makes any more.
>>>>
>>>
>>> It's for VGA (that's why it has sync and blank input)
>>> While VGA is old I doubt it is going anywhere soon, it still widely
>>> used, go buy a server and it has VGA
>>>
>>
>> Seems silly to take digital data, convert it to analog, ship it six
>> feet, and convert it back to digital.
> 
> And why do we have those firehoses of HDMI connectors and cables? Why
> not use Ethernet or USB  out to a monitor?

HDMI  is ~10-20 times the bandwidth of regular ethernet

there are plenty of monitors that can use USB-C