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From: Robert Finch <robfi680@gmail.com>
Newsgroups: comp.arch
Subject: Re: Tonights Tradeoff - Background Execution Buffers
Date: Thu, 26 Sep 2024 04:13:12 -0400
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On 2024-09-24 4:38 p.m., MitchAlsup1 wrote:
> On Tue, 24 Sep 2024 20:03:29 +0000, Robert Finch wrote:
> 
>> Under construction: Q+ background execution buffers for the block memory
>> operations. For instance, a block store operation can be executed in the
>> background while other instructions are executing. Store operations are
>> issued when the MEM unit is not busy. Background instructions continue
>> to execute even when interrupts occur. The background operations may be
>> useful for initializing blocks of memory that are not needed right-away.
>> When the operation is issued a handle for the buffer is returned in the
>> destination register so that the status of the operation may be queried,
>> or the operation cancelled.
> 
> This is how My 66000 performs:: LDM, STM, ENTER, EXIT, MM, and MS.
> Addresses are AGENED and then a state machine over in the memory
> unit performs the required steps. {{Not usefully different than the
> divider performing the individual steps of division.}} While the
> unit performs its duties, other units can be fed and complete
> other instructions.
> 
> You just have to mark the affected registers to prevent hazards.

Q+ releases the registers right away, so things can continue on.
Q+ captures the register values at issue then does not modify the 
registers. Did not want an instruction with three updates happening. It 
keeps track of its own values. In theory anyway. Have not got to testing 
it yet. A status operation might be used to query the final operation 
results.

Altering Q+ to use 64-bit instructions and 256 registers instead of 
supporting a vector instruction set. Two pipeline stages can be removed 
then and it is a simpler design. Code density will decrease <200%. 
Relying on software to assign registers for vectors.

Also adding a predicate field to instructions. Branches are horrendously 
slow in this simple implementation. It may be faster to predicate a 
dozen instructions.