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From: "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com>
Newsgroups: comp.arch
Subject: Re: is Vax addressing sane today
Date: Fri, 4 Oct 2024 12:36:41 -0700
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On 10/3/2024 11:36 PM, Chris M. Thomasson wrote:
> On 10/3/2024 9:23 PM, George Neuner wrote:
>> On Fri, 4 Oct 2024 00:48:43 -0000 (UTC), Lawrence D'Oliveiro
>> <ldo@nz.invalid> wrote:
>>
>>> On Thu, 03 Oct 2024 06:57:54 GMT, Anton Ertl wrote:
>>>
>>>> If the RISC companies failed to keep up, they only have themselves to
>>>> blame.
>>>
>>> That’s all past history, anyway. RISC very much rules today, and it 
>>> is x86
>>> that is struggling to keep up.
>>
>> You are, of course, aware that the complex "x86" instruction set is an
>> illusion and that the hardware essentially has been a load-store RISC
>> with a complex decoder on the front end since the Pentium Pro landed
>> in 1995.
> 
> Yeah. Wrt memory barriers, one is allowed to release a spinlock on "x86" 
> with a simple store.

The fact that one can release a spinlock using a simple store means that 
its basically load-acquire release-store.

So a load will do a load then have an implied acquire barrier.

A store will do an implied release barrier then perform the store.

This release behavior is okay for releasing a spinlock with a simple 
store, MOV.


Notice that there is no implied StoreLoad type of membar, xchg aside for 
a moment. Iirc, xchg has implied LOCK prefix set.

> 
> 
> 
>>
>>
>>>> Another issue was the marketing.  The RISC companies did not want to
>>>> damage their existing high-priced workstation and server business by
>>>> providing cheap CPUs for the masses ...
>>>
>>> There was one RISC family that did indeed provide cheap CPUs for the
>>> masses, even more so than x86, and that was ARM.
>