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From: Lawrence D'Oliveiro <ldo@nz.invalid>
Newsgroups: comp.arch
Subject: Re: is Vax addressing sane today
Date: Sun, 6 Oct 2024 01:03:00 -0000 (UTC)
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On Fri, 04 Oct 2024 07:05:34 GMT, Anton Ertl wrote:

> CISC and RISC are about the instruction set, not about
> the implementation.  And even if you look at the implementation, it's
> not true: The P6 has microinstructions that are ~100 bits long, whereas
> RISCs have 32-bit and 16-bit instructions. The K7 has load-store
> microinstructions; RISCs don't have that.

Intel I think tried to spread this idea of a “RISC core” somewhere inside 
the labyrinthine complexity of its Pentium-and-later chips, in the hope 
that some of the aura attached to the term “RISC” would rub off on its 
products.

And quite a few people fell for it.

> ... ARM A64 and RISC-V are clearly RISCs.

ARM and some other RISC architectures (e.g. POWER) do somewhat stretch the 
term though, don’t they, when they add that combinatorial explosion of 
operand types in their short-vector instructions.

RISC-V has consciously avoided this, by going back to the older long-
vector idea, like Seymour Cray used in his machines.

> The possibility of trapping during
> REP MOVS (or the VAX variant) complicates things, though: the first part
> of the REP MOVS has to be committed, and the registers written to the
> architectural state, and then execution has to start again with the REP
> MOVS.  Does not seem much harder on the VAX to me, however.

This is why the VAX has the “FPD” (“First Part Done”) processor status 
bit.