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From: "Edward Rawde" <invalid@invalid.invalid>
Newsgroups: sci.electronics.design
Subject: Re: Programming Languages
Date: Sat, 2 Nov 2024 13:07:32 -0400
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"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vg4fff$3lok1$1@dont-email.me...
> On 2/11/2024 12:01 pm, Edward Rawde wrote:
>> "Cursitor Doom" <cd999666@notformail.com> wrote in message news:vg3575$3bio0$1@dont-email.me...
>>> You can call me old fashioned, but I still believe there's never been a
>>> more elegant computer language than the original K&R C. You can keep the
>>> rest; I'll stick with that.
>>
>> Having just got back from a vacation I thought I'd give my input to this before looking into whether it's worthwhile getting back
>> into sinewave oscillators.
>
> John May has come up with a much better sine wave oscillator than yours.

That's no surprise. I can remember one or two other occasions when I thought I had a brilliant way to do it but someone else came up 
with a better way.
I don't specifically mean sinewave oscillators.

> It also has more components, and I'm not sure that all of them are strictly necessary. Getting deep enough into the design to be 
> sure where the harmonics are coming from is going to be difficult. I think I'm getting there, but I'm not all that motivated to 
> put in the rest of the
> work.
>
> One obvious point is that a FET channel isn't a perfect resistor - as the voltage across it rises above zero it starts looking 
> more like a constant current diode (and you can buy FET-based constant current diodes).
>
> In theory, if you added a second harmonic component to the FET gate drive you could make it look like a resistor over a wider 
> range of voltage, if the phasing was close enough to right.
>
> You've also got the point that when there's a voltage drop across the FET channel, it adds to the gate-to-channel voltage (as has 
> been mentioned here) and you can cancel that with an in-phase fundamental component

The last circuit of my own had both an n fet and a p fet.
I found that by adding a capacitor from one gate to the other (to try to cancel the unwanted signals in opposite phase) I could get 
the unwanted gate signal below 100uV. I then had harmonics approaching 60dB down except one at 50dB (I think 2KHz). Not brilliant 
but not bad.

There are some useful pointers here:
https://sound-au.com/articles/sinewave.htm
In particular where it says "Done properly, a JFET can provide distortion performance that is as good or better than a lamp or 
thermistor."

Perhaps I'll concentrate on how to make the FET behave as a voltage variable resistor over the widest possible range.

I also what to look into what I meant by crud and non crud mode in LTSpice.
This mysterious effect can depend on things such as which specific computer is used and how long is specified before collecting 
simulation data.
You can see it in the gate voltage after startup. It looks a bit like a PLL hunting and eventually locking but it doesn't happen at 
startup, it happens after seconds.
So I'll need to be able to post some pictures to show that. I'll get to that.

Is there an easy way to remove a DC offset from a simulation trace so that my n and p gate signals can be superimposed after 
startup?

>
> -- 
> Bill Sloman, Sydney
>