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From: "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com>
Newsgroups: comp.arch
Subject: Re: Arm ldaxr / stxr loop question
Date: Fri, 8 Nov 2024 14:56:51 -0800
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On 11/8/2024 2:45 PM, Scott Lurndal wrote:
> "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> writes:
>> On 11/2/2024 12:10 PM, Chris M. Thomasson wrote:
>>> On 11/1/2024 9:17 AM, aph@littlepinkcloud.invalid wrote:
>>>> jseigh <jseigh_es00@xemaps.com> wrote:
>>>>> So if were to implement a spinlock using the above instructions
>>>>> something along the lines of
> 
>>
>> Fwiw, I am basically asking if the "store" stxr has implied acquire
>> semantics wrt the "load" ldaxr? I am guess that it does... This would
>> imply that the acquire membar (#LoadStore | #LoadLoad) would be
>> respected by the store at stxr wrt its "attached?" load wrt ldaxr?
>>
>> Is this basically right? Or, what am I missing here? Thanks.
>>
>> The membar logic wrt acquire needs to occur _after_ the atomic logic
>> that locks the spinlock. A release barrier (#LoadStore | #StoreStore)
>> needs to occur _before_ the atomic logic that unlocks said spinlock.
>>
>> Am I missing anything wrt ARM? ;^o
> 
> Did you read the extensive description of memory semantics
> in the ARMv8 ARM?   See page 275 in DDI0487K_a.
> 
> https://developer.arm.com/documentation/ddi0487/ka/?lang=en

I did not! So I am flying a mostly blind here. I don't really have any 
experience with how ARM handles these types of things. Just guessing 
that the store would honor the acquire of the load? Or, does the store 
need a membar and the load does not need acquire at all? I know that the 
membar should be after the final store that actually locks the spinlock 
wrt Joe's example.

I just need to RTFM!!!!

Sorry about that Scott. ;^o

Perhaps sometime tonight. Is seems like optimistic LL/SC instead of 
pessimistic CAS RMW type of logic?