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Path: ...!weretis.net!feeder9.news.weretis.net!tncsrv06.tnetconsulting.net!usenet.blueworldhosting.com!diablo1.usenet.blueworldhosting.com!nnrp.usenet.blueworldhosting.com!.POSTED!not-for-mail From: "Edward Rawde" <invalid@invalid.invalid> Newsgroups: sci.electronics.design Subject: Re: Final final 1kHz oscillator Date: Sun, 17 Nov 2024 22:58:58 -0500 Organization: BWH Usenet Archive (https://usenet.blueworldhosting.com) Lines: 55 Message-ID: <vhee22$10q2$1@nnrp.usenet.blueworldhosting.com> References: <vglt5t$30a3$1@nnrp.usenet.blueworldhosting.com> <t5fajjdteskfftvkf84iqsp2vc4b9ta5kj@4ax.com> <vh57l4$2knt$1@nnrp.usenet.blueworldhosting.com> <n7iijjdeqecl0kmub0bq5in0dbm60m7qam@4ax.com> Injection-Date: Mon, 18 Nov 2024 03:58:58 -0000 (UTC) Injection-Info: nnrp.usenet.blueworldhosting.com; logging-data="33602"; mail-complaints-to="usenet@blueworldhosting.com" Cancel-Lock: sha1:bVdRtknJqlrZtNl9kCelGJwJWPk= sha256:om+aNXfY9qfdcxc52vN0RbivOBnNcFBhlDlOYYCn1KI= sha1:PgPsPGtyyCTZsgda1bmc0PaLhcg= sha256:raVJkXkNoTp3mQ+5RPEFttubjw6dluhd90NXOHxAu7c= X-Newsreader: Microsoft Outlook Express 6.00.2900.5931 X-Priority: 3 X-RFC2646: Format=Flowed; Original X-MSMail-Priority: Normal X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.6157 Bytes: 3799 "JM" <sunaecoNoChoppedPork@gmail.com> wrote in message news:n7iijjdeqecl0kmub0bq5in0dbm60m7qam@4ax.com... > On Thu, 14 Nov 2024 11:14:28 -0500, "Edward Rawde" > <invalid@invalid.invalid> wrote: > >>"JM" <sunaecoNoChoppedPork@gmail.com> wrote in message news:t5fajjdteskfftvkf84iqsp2vc4b9ta5kj@4ax.com... >>> On Fri, 8 Nov 2024 15:43:41 -0500, "Edward Rawde" >>> <invalid@invalid.invalid> wrote: >>> >>>>This is the simplest circuit I can come up with. .... >>>> >>> >>> Using an NSL-32SR3 doesn't really gain you anything over a FET. If >>> you keep |vds| much less than |Vt-vgs| in the circuit and compensate >>> for the vds/2 variation on the gate drive the distortion levels >>> produced will be lower than almost all opamps out there. Here's a >>> link to a sim using an LDR. >>> >>> https://1drv.ms/f/c/1af24d72a509cd48/EkjNCaVyTfIggBrrAQAAAAABHXNKs52BoVHi7zaxKmdMMQ?e=oVD0JS >>> >>> I've added some 3rd harmonic distortion to a linear model to give >>> distortion figures roughly in the ballpark of Fig 6 in the attached >>> application note (for small signal swings across the device). In the >>> oscillator o/p the 3rd is about 150dB down. If you use the linear LDR >>> model, or a FET, it will be much the same. (The opamps used in the sim >>> actually have distortions specs of about 130dB in reallity.) >> >>Thanks for that. I left it overnight for 100 seconds of simulation. It looks like it has better harmonic performance than my >>circuit. >>Why use two op amps in the oscillator instead of one like my circuit? > > Because of common mode (non)linearity. In most op-amps (especially > older designs) the distortion generated by the common mode signal is > typically one to two orders of magnitude larger than the transfer > distortion. If it is not clear from the data sheet, it is best to > measure the CM performance or just assume that it's 40dB worse than > the specified figure. > > Note that it is seldom modeled in a (free) spice model. > > This is a link to an extract discussing it's measurement. > > https://1drv.ms/u/c/1af24d72a509cd48/ESErQT4Elb5FsgcgsOp1J3wBWZSYHvooHblQJPA3DmydbA?e=wwqtSy Thank you very much for that information. > >>What happens without the initial conditions? Does it take a long time to settle? >>I'll be away until next week. >> > > No idea. LTSpice is useless for handling large simulation data files > so I don't bother trying to use it to check for that sort of thing.