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From: John Levine <johnl@taugh.com>
Newsgroups: comp.arch
Subject: Re: Keeping other stuff with addresses (was: What is an N-bit machine?)
Date: Sat, 30 Nov 2024 19:12:13 -0000 (UTC)
Organization: Taughannock Networks
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References: <memo.20241128153105.12904U@jgd.cix.co.uk> <2024Nov30.175756@mips.complang.tuwien.ac.at> <20241130193206.00005c49@yahoo.com> <2024Nov30.190858@mips.complang.tuwien.ac.at>
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According to Anton Ertl <anton@mips.complang.tuwien.ac.at>:
>>> >>>>These days I'd say the relevant N is the size of arithmetic
>>> >>>>registers but a lot of marketers appear to disagree with me.  

>The widest arithmetic registers on AMD64 with AVX-512 are the ZMM
>registers with 512 bits each.  Sure, they are used for arithmetic on a
>sequence of individually narrower data, but the registers have 512
>bits nonetheless.

Jeez, who knew you were a chip salesman.

I meant the main registers, for some straightforward version of main.
You are of course correct that there are special purpose registers
that are much wider but I don't think it's all that hard to see which
ones I meant.

Everyone agreed that all the models of S/360 were 32 bit machines, but the
implementations ranged from 8 bits for the /25 and /30 to 64 bits for
the /75.  I don't think it's very useful to argue about whether the various
models of 360 were 8, 16, 32, or 64 bit machines.

-- 
Regards,
John Levine, johnl@taugh.com, Primary Perpetrator of "The Internet for Dummies",
Please consider the environment before reading this e-mail. https://jl.ly