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From: Gerhard Hoffmann <dk4xp@arcor.de>
Newsgroups: sci.electronics.design
Subject: Re: DDS follies
Date: Sat, 7 Dec 2024 12:24:57 +0100
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Am 07.12.24 um 00:01 schrieb john larkin:

>>> https://highlandtechnology.com/Product/V375
>>>
>>> It has four DDS clock synthesizers; I used AD9830s and fancy LC
>>> filters and comparators for the clocks. They have 32-bit frequency set
>>> registers and I'm clocking at 40 MHz, max out 15 MHz.
>>>
>>> The design is 22 years old and, amazingly, 2024 has been its best
>>> selling year ever. But all sorts of stuff is going EOL so I have to
>>> redesign it. I can go from 7 FPGAs and many SRAMs to one Efinix with
>>> all the waveform memories on-chip.

>> afaict the AD9830 is just a phase accumulator and a lookup table, you
>> should be able to do that quite a bit faster than 40MHz in an FPGA

> I have to  make the 32-bit DDS look like it has a 40 MHz clock, for
> compatibility with older products.
> 
> So why have sine tables and DACs and filters and comparators? Why not
> use the MSB of the phase accumulator as my system clock? I can
> synthesize one octave and divide down below that.
> 
> It might be possible to spin a faster clock and make a digital filter,
> esentially, lowpass the accumulator triangle waveform to reduce
> jitter; too much work.
> 
> I can't see the virtue of a sine lookup. The phase accumulator makes a
> triangle and, near the zero crossing, a sine wave looks just like a
> triangle. Well, it's 2*pi steeper, but a zero crossing comparator
> isn't impressed by that.
> 
> Why take a perfectly beautiful triangle and spin the poor thing all
> around in a circle?
> 

I published a DDS maybe 15 years ago. It ran at CLK = 230 MHz including
sine table in a Spartan-6 on a SP605 eval board. If you don't want the
sine table, leave it away. That won't make it slower :-)
It is pure VHDL, no Matlab or Xilinx macros.

<    http://opencores.org/project,sincos   >

The number of pipeline stages (0..10) and resolution can be set by
a constant, output width(s)is taken automagically by the buses that
are connected.
The sine ROM has only 90°, mirroring etc included. sin/cos outputs are
available at the same time yet do not need another ROM.

I needed it for an all-digital PLL, so a Cordic with it's long delays
was not an option.

cheers, Gerhard