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From: Marcus <m.delete@this.bitsnbites.eu>
Newsgroups: comp.arch
Subject: What do we call non-pipelined designs?
Date: Sun, 8 Dec 2024 23:10:15 +0100
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I usually (and simplistically) divide CPU designs (implementations) into
two main categories:

- Pipelined
- Non-pipelined

Of course, there is a sliding scale at play, but let's not get into that
debate.

My question is: What is the best name for non-pipelined designs?

I'm thinking about CPU:s that transition through several states (one
clock cycle after another) when executing a single instruction (e.g.
FETCH + DECODE + EXECUTE), and where instruction and data typically
share the same memory interface.

/Marcus