Path: ...!news.mixmin.net!weretis.net!feeder8.news.weretis.net!newsfeed.bofh.team!paganini.bofh.team!not-for-mail
From: antispam@fricas.org (Waldek Hebisch)
Newsgroups: comp.lang.c
Subject: Re: question about linker
Date: Wed, 11 Dec 2024 23:33:48 -0000 (UTC)
Organization: To protect and to server
Message-ID: <vjd7gq$1cdcv$1@paganini.bofh.team>
References: <vi54e9$3ie0o$1@dont-email.me>   <viasv4$nm7q$2@dont-email.me> <vibr1l$vvjf$1@dont-email.me> <vic73f$1205f$1@dont-email.me> <20241129142810.00007920@yahoo.com> <vicfra$13nl4$1@dont-email.me> <20241129161517.000010b8@yahoo.com> <vicque$15ium$2@dont-email.me> <vid110$16hte$1@dont-email.me> <vifcll$1q9rj$1@dont-email.me> <vifiib$1s07p$1@dont-email.me> <viht27$2hgg1$3@dont-email.me> <vjb8e9$1973q$1@paganini.bofh.team> <20241211111856.00005d14@yahoo.com> <vjbunl$1h46m$1@dont-email.me>
Injection-Date: Wed, 11 Dec 2024 23:33:48 -0000 (UTC)
Injection-Info: paganini.bofh.team; logging-data="1455519"; posting-host="WwiNTD3IIceGeoS5hCc4+A.user.paganini.bofh.team"; mail-complaints-to="usenet@bofh.team"; posting-account="9dIQLXBM7WM9KzA+yjdR4A";
User-Agent: tin/2.6.2-20221225 ("Pittyvaich") (Linux/6.1.0-9-amd64 (x86_64))
X-Notice: Filtered by postfilter v. 0.9.3
Bytes: 3781
Lines: 52

bart <bc@freeuk.com> wrote:
> On 11/12/2024 09:18, Michael S wrote:
>> On Wed, 11 Dec 2024 05:37:15 -0000 (UTC)
>> antispam@fricas.org (Waldek Hebisch) wrote:
> 
> I remember running TCC on both RPi1 (2012) and RPi4 (2019). That would 
> be ARM32 (some version of ARMv7 I guess; I find ARM model numbers 
> bewildering).
> 
> It's possible I also tried TCC in the ARM64 mode of RPi4.
> 
> So it sounds rather unlikely that TCC doesn't support ARM.

To add to what Michael S wrote: AFAICS TCC can generate code
for ARM version 5.  This is 32-bit ARM instructions set and
should work on all reasonably new (sey less than 25 years
old) non-embedded ARM processors supporting 32-bit instructions.
TCC can also generate instructions for 64-bit ARM (usually
called aarch64).  AFAICS it does not support Thumb instruction
set which is used in popular Cortex-M series.  Some old
embedded processors use 32-bit ARM instructions, but
there are restrictions and chance that tcc compiled code will
work on embedded processor is not big.  And even if it works,
32-bit instructions give significantly bigger code than
Thumb encoding, and that on top of bigger code size from
tcc.  So even, if tcc code could work, it is rather unattractive.

Let me add that MCU-s typically support only a subset of
ARM/Thumb instructions.  For example, still quite popular
is Cortex-M0.  It supports only Thumb1 instructions which
are quite limited.  Basically, if processor supports more
instructions you want to use additional instructions, as that
makes code significantly faster.  Cortex-M3 and Cortex-M4
are better, but IIRC still lacks some Thumb instructions
present in bigger processors.  And bigger processors can
switch between Thumb and 32-bit encoding, while Cortex-M
is Thumb-only.

There are now embedded Risc-V processors.  But Risc-V can
be 32-bit or 64-bit.  Embedded Risc-V processors are
32-bit, while IIUC tcc supports only 64-bit Risc-V.
There are also intermediate-style machines.  They support
64-bit instructions, but have small memory that comfortably
could be addressed using 32-bit.  For such a machine it makes
sense to use 64-bit instructions, but use 32-bit pointers and
long.  gcc and clang support such mode for Intel/AMD
processors under name x86_64-x32.  It seems that no
mainstream compiler supports similar mode for Risc-V
(there is some talk, so maybe one can find some experimental
support).

-- 
                              Waldek Hebisch