Path: ...!weretis.net!feeder8.news.weretis.net!newsfeed.bofh.team!paganini.bofh.team!not-for-mail
From: antispam@fricas.org (Waldek Hebisch)
Newsgroups: comp.arch
Subject: Re: What is an N-bit machine?
Date: Mon, 16 Dec 2024 22:39:18 -0000 (UTC)
Organization: To protect and to server
Message-ID: <vjqa6k$2q4op$1@paganini.bofh.team>
References: <memo.20241128153105.12904U@jgd.cix.co.uk> <2024Nov30.175756@mips.complang.tuwien.ac.at> <20241130193206.00005c49@yahoo.com> <2024Nov30.190858@mips.complang.tuwien.ac.at> <vifo2d$19lu$1@gal.iecc.com> <2024Dec1.094117@mips.complang.tuwien.ac.at>
Injection-Date: Mon, 16 Dec 2024 22:39:18 -0000 (UTC)
Injection-Info: paganini.bofh.team; logging-data="2954009"; posting-host="WwiNTD3IIceGeoS5hCc4+A.user.paganini.bofh.team"; mail-complaints-to="usenet@bofh.team"; posting-account="9dIQLXBM7WM9KzA+yjdR4A";
User-Agent: tin/2.6.2-20221225 ("Pittyvaich") (Linux/6.1.0-9-amd64 (x86_64))
X-Notice: Filtered by postfilter v. 0.9.3
Bytes: 9541
Lines: 171

Anton Ertl <anton@mips.complang.tuwien.ac.at> wrote:
> John Levine <johnl@taugh.com> writes:
>>I meant the main registers, for some straightforward version of main.
>>You are of course correct that there are special purpose registers
>>that are much wider but I don't think it's all that hard to see which
>>ones I meant.
> 
> I guess you mean the general-purpose registers, which is not a proper
> definition, either, and it means that the criterion only applies to
> architectures with general-purpose registers.
> 
> I tried to be more precise and as a criterion "address register size",
> i.e., the size of a register that holds an address.  And I guess that
> should be refined to the size of a register that holds one address (to
> avoid the issue of vector registers containing addresses for
> scatter/gather instructions).  This also makes it clear that this
> criterion does not apply to machines like the IBM 704 and PDP-10 that
> have two addresses per machine word, but for word-addressed machines
> the word size makes it clear what is meant with "N-bit machine".  This
> resulta in:
> 
> 1) For word-addressed machines: the size of the word.
> 
> 2) For byte-addressed machines: the size of a register that contains
> one address.
> 
> These criteria agree with the usual understanding of the bitness of an
> architecture for most architectures, with a few exceptions:
> 
> * The 68000 would be classified as 32-bit architecture, which agrees
>   with the modern understanding, but not with the marketing as 16-bit
>   CPU or 16/32-bit CPU at the time.
> 
> * Most CPUs described as 8-bit CPUs keep at least the program counter
>   in a larger register, a number of them (6800, 8008 and its
>   descendents) also have 16-bit data-address registers or
>   register-pairs (at least HL for the 8008).  At the time they and the
>   68000 were described as 8-bit (16-bit for the 68000) based on the
>   implementation of having an 8-bit data bus, but that argument broke
>   down with the 8088 and 68008.
> 
> * I am not that familiar with the old character-oriented
>   architectures, such as the IBM 702; they apparently are not
>   described as N-bit machines for any N, so we probably don't need to
>   assign such a label to them nowadays.

I am not familiar with IBM 702, but IBM 1401 is in a sense more
"interesting"

- core is read in 7 bit units (8 bit if you count parity which
  in only used for error checking).  6 bits are data bit, one
  is "word mark" playing important role in the architecture.
- there is single 6 bit data register, capable of holding a
  single character.
- arithmetic is done on 4-bit BCD digits.  IIRC usually non-digit
  characters in arithmetic are errors, but sometimes have spacial
  meaning.
- there are 2 address register, each 3 characters long.  Similarly
  3 memory locations each 3 characters long _may_ be designated
  as "index registers" (that was separately charged feature).
  Of course there is also program counter.
- instructions primary effect is on memory where they operate
  on variable length "words" usually delimited by "word marks".
  I do not remember is data register is programmer visible, but
  address registes are visible.
- instructions have variable length, from 1 to 8 characters.
  Normally end of instructions is signalled by "word mark".
- actual memory addresses are decimal up 16000 - 1, but use
  funky encoding.  Two bits are used to specify "index register".

There are later models which can use longer addreses and change
address length.

There was also Honeywell 200 which borrowed several parts of
1401 architecture, but added one more mark bit and switched to
purely binary addressing.  IIRC Honeywell 200 cound be switched
between 2 character (12 bit), 3 character and 4 character
addresses.  The last two version used 3 bit to choose index
register.

There were several other low-end "commercial" machines with
more or less strange arrangements.  One of Polish machines
used 16-bit core words and 16-bit instructions, had some
16-bit registers, but also 16-digit "accumulator" working
in BCD encoding.  So one could view it as 16-bit machine
or 16-digit machine (but decimal arithmetic could use
varying length, 16 digit was max of what hardware could
do directly).

> * There were also fixed-word-length machines that were not binary,
>   such as the IBM 7070.  Memory is described as consisting of words,
>   so criterion 1 can be applied, except that it's not N-bit, but
>   N-digit.
> 
> Anything else?
> 
> BTW, note that these are architectural (i.e., instruction-set-related)
> criteria; an implementation can implement several instruction sets.
> E.g., I can run programs for the 16-bit 8086 architecture, for the
> 32-bit IA-32 architecture and for the 64-bit AMD64 architecture on,
> e.g., the recent AMD Ryzen 9 9950X and the Intel Core Ultra 9 285K.
> 
>>Everyone agreed that all the models of S/360 were 32 bit machines, but the
>>implementations ranged from 8 bits for the /25 and /30 to 64 bits for
>>the /75.
> 
> This sentence is contradictory.  All these implementations have 32-bit
> general-purpose registers (otherwise they would not be S/360
> implementations), which are address registers, and are therefore
> 32-bit architectures by your and my criteria.
> 
> You obviously mean something different about these implementations.
> What is it?

IIUC from hardware point of view 360/20, 360/25 and corresponding
model in 370 family were micros with rathere short word which
IBM equipped with emulation program which emulated 360 instruction
set.  I do not remember exact details for each of them, but at
least one executed emulation program ("microcode") from the same
16-bit physical core are "360 memory".  360 architectural registers
were just locations in core.  IIUC running programs on real
 hardware was unsupported by IBM, but nothing technically stopped
customers from doing this.  A research team created experimental
Fortran compiler targeting the hardware and they reported that
programs compiled by their Fortran run 45 times faster than
IBM Fortran compiling to 360 instruction set which was then
interpreted by "microcode".

360/30 had 8-bit date bus and mixture of 8 and 16-bit registers.
Here microcode was stored in capacitove read-only memory, had
longish words (something like 60-bits) and microcode memory
access was 5 times faster than core access time.  Again,
360 architectural registers were stored in core memory (some
IBM models had faster "local core", I do not remember if
360/30 stored registers in "local core" or main core).

In 360/30 microcode memory was read-only, so unlike 2x models
was not usable to load programs or store data, but at least
in principle could be changed by users.  Namely, capacitive
memory used flat foil capacitors, with data correspondig
to pattern on conductive fields on the foil.  Simple tools
allowed to remove fields form "full" (or if you prefer "blank")
foil and in this way program desired content.

So, main difference between 2x models and modern machine
running an emulator (like Hercules) was that IBM said that
360 instruction set was "native" on 2x models (but 1401
mode was as native as 360 mode, one simply loaded different
IBM-provided emulation program).  If one takes IBM word
that 2x models hardware implements 360 instruction set
at face value, then I think one should also take vendor
claims of "bitness" at face value.  If one digs deeper,
then 2x models are 16 bit (or someting like mixed 16/19
bit) architecture emulating 32-bit architecture.

IIUC at that time some people made distinction between
processor (that is official user-visible thing) and
microprocessor (actual hardware).  First semicondutior
microprocessors were intended to be microprocessors in
this sense, that is to be used to implement different
user visible aspect.  In this spirit native architecture
of many home computers would be BASIC.  However, running
directly on microprocessor gives large performance benefits
so this was used by lot of sofware and hardware instruction
set was considerd as native one.  The old view lives in
IBM AS/400 series or whatever IBM calls their successors:
AFAICS "official" instruction set of those machines is
implemented by software and actual hardware is quit different
and may vary.

-- 
                              Waldek Hebisch