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From: jseigh <jseigh_es00@xemaps.com>
Newsgroups: comp.arch
Subject: Re: Strange asm generated by GCC...
Date: Fri, 20 Dec 2024 14:59:36 -0500
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On 12/20/24 12:46, jseigh wrote:
> On 12/19/24 19:43, Chris M. Thomasson wrote:
>> Why in the world would GCC use an XCHG instruction for the following 
>> code. The damn XCHG has an implied LOCK prefix! Yikes!
>>
> 
> Speaking of strange code
> 
That should be a ref paramter.  I though I updated the pasted code.

#include <atomic>

bool test1(std::atomic<int>& var, int addend)
{
     int expected = var.load(std::memory_order_relaxed);
     int update = expected + addend;
     return var.compare_exchange_weak(expected, update, 
std::memory_order_acq_rel, std::memory_order_seq_cst);
}

test1(std::atomic<int>&, int):                 // 
@test1(std::atomic<int>&, int)
         ldr     w8, [x0]
         ldaxr   w9, [x0]
         cmp     w9, w8
         b.ne    .LBB0_3
         add     w8, w8, w1
         stlxr   w9, w8, [x0]
         cbz     w9, .LBB0_4
         mov     w0, wzr
         ret
..LBB0_3:
         clrex
         mov     w0, wzr
         ret
..LBB0_4:
         mov     w0, #1
         ret