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Path: ...!feeder3.eternal-september.org!news.eternal-september.org!eternal-september.org!.POSTED!not-for-mail From: Thomas Koenig <tkoenig@netcologne.de> Newsgroups: comp.arch Subject: Re: Interview with Power's chief designer Date: Mon, 30 Dec 2024 14:27:17 -0000 (UTC) Organization: A noiseless patient Spider Lines: 44 Message-ID: <vkuak5$1logs$1@dont-email.me> References: <vkma3i$3kfu7$1@dont-email.me> <c1296edb05377780f84d594d38be1e85@www.novabbs.org> <20241229144846.00004de6@yahoo.com> Injection-Date: Mon, 30 Dec 2024 15:27:18 +0100 (CET) Injection-Info: dont-email.me; posting-host="db0765b26d4bbc5fa32b8e2da465db3b"; logging-data="1761820"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19EohqnlaYo1OI5NJ320cc54oWr0bvMQZ4=" User-Agent: slrn/1.0.3 (Linux) Cancel-Lock: sha1:xDNwPkYzGPJ+wew/ptMWDwE7Rxw= Bytes: 2928 Michael S <already5chosen@yahoo.com> schrieb: > On Sun, 29 Dec 2024 01:58:52 +0000 > mitchalsup@aol.com (MitchAlsup1) wrote: > >> On Fri, 27 Dec 2024 13:29:22 +0000, Thomas Koenig wrote: >> >> > Not sure how many of you read Chips and Cheese, but in case you're >> > interested: Here is an inteview with IBM Power's chief designer, >> > Bill Starke: >> > >> > https://old.chipsandcheese.com/2024/12/26/ibm-power-whats-next/ >> > >> > There is a lot of talk on OMI (he really doesn't like DDR, and gives >> > reasons, especially the amount of memory and reliability), plus some >> > detail on POWER11, which apparently will be a microarchitectural >> > evolution, but no new ISA parts, and the philosophy behind the >> > chiplet design they are about to do for the next generation after >> > that. >> >> He makes a compelling point that DDR is using too many pins and >> still does not provide the desired BW available for that number >> pf pins. And that a SEREDS interface to DRAMs provide easier to >> achieve signaling and larger memories at the same time--similar >> to what CXL:memory is attempting. >> > > Unlike CXL:memory, OMI is not layered on top PCIe gen5 phy. > They claim the same bandwidth with lower latency and lower power. Interestingly enogh (I only found this when looking) OMI appears to have been absorbed by CXL. You can find the OpenCAPI specs, which OMI is based on, at https://computeexpresslink.org/resource/opencapi-specification-archive/ > I don't know where to looks for details of physical layer of OMI, but > would suspect that it is more like HyperTransport or Intel QPI/UPI than > like PCIe. I.e. timing, including phase, is not recovered independently > from every data lane, but provided as a dedicated signal. Likely one > timing signal per group of 4 or 5 data signals. > All above are my speculations not based on knowledge. If you're so inclined, you can wade through the specs, but it's likely a non-trivial amount of work...