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From: Marcus <m.delete@this.bitsnbites.eu>
Newsgroups: comp.arch
Subject: Re: What do we call non-pipelined designs?
Date: Sat, 11 Jan 2025 19:13:50 +0100
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On 2024-12-26, Robert Finch wrote:
> On 2024-12-08 5:10 p.m., Marcus wrote:
>> I usually (and simplistically) divide CPU designs (implementations) into
>> two main categories:
>>
>> - Pipelined
>> - Non-pipelined
>>
>> Of course, there is a sliding scale at play, but let's not get into that
>> debate.
>>
>> My question is: What is the best name for non-pipelined designs?
>>
>> I'm thinking about CPU:s that transition through several states (one
>> clock cycle after another) when executing a single instruction (e.g.
>> FETCH + DECODE + EXECUTE), and where instruction and data typically
>> share the same memory interface.
>>
>> /Marcus
> According to my understanding of  “pipelined” most designs are 
> pipelined. There are not very many non-pipelined designs.

True. I'm talking about a niche here.

> Non-pipelined designs perform everything in one long clock cycle.

The designs I'm thinking about are mostly multi-cycle, i.e. one
instruction takes several cycles to complete.

> Otherwise, there are two major classes of pipelined designs,
> non-overlapped pipeline and overlapped pipeline. Some designs are
> partially overlapped pipelined.

For the sake of the argument, what should we call:

* Intel 8008 [1]
* Olof Kindgren's SERV [2]
* MOS 6502 [3]

?

There may be some pipelining in parts of these designs, but the key
point I'm trying to get at is that the CPU typically goes through a
sequence of states when executing an instruction, and it is typically
"busy" for more than one clock cycle while executing one instruction.

/Marcus

[1] https://en.wikipedia.org/wiki/Intel_8008
[2] 
https://serv.readthedocs.io/en/latest/internals.html#instruction-life-cycle
[3] https://en.wikipedia.org/wiki/MOS_Technology_6502