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From: "Edward Rawde" <invalid@invalid.invalid>
Newsgroups: sci.electronics.design
Subject: Re: Current mirror version of the lowish distortion 1kHz sine wave osillator
Date: Wed, 15 Jan 2025 14:47:39 -0500
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"Edward Rawde" <invalid@invalid.invalid> wrote in message news:vm8u2l$pns$1@nnrp.usenet.blueworldhosting.com...
> "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vm89vp$2ulja$1@dont-email.me...
>> This just reworks my circuit to use a controllable asymmetric current mirror instead of the FET for gain control. I take the 
>> feedback from the full wave rectifier and switch every half-cycle to reconstruct a variable amplitude sine wave to control the 
>> output amplitude. It does use a lot of components, but it strikes me as fairly comprehensible.
>>
>
> First I corrected the usual line wrap issues.
>
> In the latest LTSpice (24.1.0) it took me a good hour or two to find out why I was getting strange netlist errors for all the 
> opamps in the circuit.
>
> This turned out to be .ENDS in the BAS70L model. Remove .ENDS and the issues go away.
>
> So this is the circuit I'm simulating in 24.1.0 with no component updates available.
> I'm expecting it to take 2 hours to complete.

Actually I was wrong about the simulation time.
For 10 seconds the simulation time will be between 5 and 7 days.