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<vm9c8s$pe1$1@nnrp.usenet.blueworldhosting.com> View for Bookmarking (what is this?) Look up another Usenet article |
Path: ...!weretis.net!feeder9.news.weretis.net!newsfeed.hasname.com!usenet.blueworldhosting.com!diablo1.usenet.blueworldhosting.com!nnrp.usenet.blueworldhosting.com!.POSTED!not-for-mail From: "Edward Rawde" <invalid@invalid.invalid> Newsgroups: sci.electronics.design Subject: Re: Current mirror version of the lowish distortion 1kHz sine wave osillator Date: Wed, 15 Jan 2025 17:19:07 -0500 Organization: BWH Usenet Archive (https://usenet.blueworldhosting.com) Lines: 800 Message-ID: <vm9c8s$pe1$1@nnrp.usenet.blueworldhosting.com> References: <vm89vp$2ulja$1@dont-email.me> <vm8u2l$pns$1@nnrp.usenet.blueworldhosting.com> <vm93ct$vf9$1@nnrp.usenet.blueworldhosting.com> Injection-Date: Wed, 15 Jan 2025 22:19:08 -0000 (UTC) Injection-Info: nnrp.usenet.blueworldhosting.com; logging-data="26049"; mail-complaints-to="usenet@blueworldhosting.com" Cancel-Lock: sha1:B+6+y1Nvk13sJ5e6oZyL/y2B98s= sha256:Nr0mV1EaCLpLEM+EQcG0fm0YE7bgcxaBE6hW9ZS3rXE= sha1:AyhiFIQ3M5Y2khka4v4iONNknKc= sha256:y4CFNwftylmdpHxdT3ZqbsvyANEJKc//sRNwy8kPtkg= X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.6157 X-RFC2646: Format=Flowed; Response X-MSMail-Priority: Normal X-Priority: 3 X-Newsreader: Microsoft Outlook Express 6.00.2900.5931 Bytes: 23578 "Edward Rawde" <invalid@invalid.invalid> wrote in message news:vm93ct$vf9$1@nnrp.usenet.blueworldhosting.com... > "Edward Rawde" <invalid@invalid.invalid> wrote in message news:vm8u2l$pns$1@nnrp.usenet.blueworldhosting.com... >> "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vm89vp$2ulja$1@dont-email.me... >>> This just reworks my circuit to use a controllable asymmetric current mirror instead of the FET for gain control. I take the >>> feedback from the full wave rectifier and switch every half-cycle to reconstruct a variable amplitude sine wave to control the >>> output amplitude. It does use a lot of components, but it strikes me as fairly comprehensible. >>> >> >> First I corrected the usual line wrap issues. >> >> In the latest LTSpice (24.1.0) it took me a good hour or two to find out why I was getting strange netlist errors for all the >> opamps in the circuit. >> >> This turned out to be .ENDS in the BAS70L model. Remove .ENDS and the issues go away. >> >> So this is the circuit I'm simulating in 24.1.0 with no component updates available. >> I'm expecting it to take 2 hours to complete. > > Actually I was wrong about the simulation time. > For 10 seconds the simulation time will be between 5 and 7 days. > There was a mistake in the corrected circuit I posted which was caused by me investigating why it wouldn't simulate at all in 24.1.0 U6 and U7 power was disconnected. But it still looks like 4 days for 10 seconds. The circuit below should be what Bill intended. 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