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From: "Edward Rawde" <invalid@invalid.invalid>
Newsgroups: sci.electronics.design
Subject: Re: Current mirror version of the lowish distortion 1kHz sine wave osillator
Date: Tue, 21 Jan 2025 11:08:46 -0500
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"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vmninh$3t6oi$1@dont-email.me...
> On 21/01/2025 2:19 am, Bill Sloman wrote:
>> On 15/01/2025 11:33 pm, Bill Sloman wrote:
>>> This just reworks my circuit to use a controllable asymmetric current mirror instead of the FET for gain control. I take the 
>>> feedback from the full wave rectifier and switch every half-cycle to reconstruct a variable amplitude sine wave to control the 
>>> output amplitude. It does use a lot of components, but it strikes me as fairly comprehensible.
>>>
>>> R30 isn't a real part - it's just there to let me do an FFT on the correction signal.
>>>
>>> The circuit just copes with worst case capacitors - 15.15nF and 14.85nF - at C5 and C6, as it was intended to do. Using a trim 
>>> pot to take out component tolerances would let you get away with a smaller correction signal injecting smaller doses of the odd 
>>> harmonics.
>>>
>>> The circuit does cry out for monolithic dual transisors.The On-Semi
>>> NST45010MW6T1G pnp and the
>>> NST45011MW6T1G npn parts are cheap and widely available.
>>
>> There was a dumb error in the original circuit. The two transistor switch (Q5 and Q6 in the original circuit) that turned the 
>> full wave rectified waveform back into a sine wave was set up with very little headroom. It didn't stop the circuit from working 
>> as intended after it had settled down, but it made start-up a bit tricky.
>>
>> Here's the corrected version. It's performance isn't noticeably different
>
> I've taken Edward Rawles commnents to heart,but I suspect he has inadvertently corrected the circuit into something that simulates 
> a lot slower that the circuit I'm looking at, which runs at about 30msec/sec.
>
> I've corrected the right transistor to Q6. I've played with the text file in an attempt deal with the line feeds.
>
> U1 is an LT1360 and Linear Technology's LTSpice should know all about that. The relevant lines in the file are
>
> "SYMBOL Opamps\\LT1360 208 -1248 R0
> SYMATTR InstName U1"
>
> The BAS70L model file below is
>
> TEXT -2232 -1200 Left 2 !.MODEL BAS70L D
> \n+ IS = 3.22E-9
> \n+ N = 1.018
> \n+ BV = 77 \n+ IBV = 1.67E-7
> \n+ RS = 20.89
> \n+ CJO = 1.608E-12
> \n+ VJ = 0.3891
> \n+ M = 0.3683
> \n+ FC = 0.5
> \n+ EG = 0.69
> \n+ XTI = 2
> \n.ENDS
>
> The \n+ character string does seem to be the way WordPad deals with line wraps in the .asc file.

It's been many years since I forgot that WordPad even exists.
Get yourself a real editor: https://notepad-plus-plus.org/
I use it for editing files on both Windows and Linux (Over WinSCP).
It may be worth noting that WordPad (which I just opened for the first time in seems like centuries) has a No wrap option under Word 
wrap.
I'd set it to No wrap before pasting it into a post.

> Deleting .ENDS from the end of the model string may be one way of keepig LTSpice happy, but it probably isn't the right one.

Then please tell us what the right way is when you get to testing LTSpice 24.1.0

>

Make new folder Sloman 21 Jan 2025
Make a new text file in the folder and rename it sloman.asc
Copy all relevant lines from post starting with Version 4
Open asc file with Notepad++ and paste lines.
Search for Elektronik
Fix 9 line wraps.
Save file and attempt to open it in LTSpice 24.0.12
Get error with \n+ IS = 3.22E-9 line.
Open asc file with Notepad++
Fix about 15 more line wraps with lines starting with \n and a few other lines.
Note \ characters in line beginning with TEXT -336 -528 Left 2 these are not present in yesterday's file.
Successfully open LTSpice to view a schematic.
Note that U1 (LT1360) is displaced upwards such that the output is pointing at the centre of the letter B in the adjacent BAS70L
Move U1 down so everything except + power is connected.
Note that U1 + power wire ends about one resistor length above the U1 symbol.
Connect U1 + power.
Start simulation and click on Vout.
Note simulation speed of about 20us/s

Stop simulation, Save file, Close LTSpice.
Open asc file with Notepad++
Check that Word wrap is off and set EOL to Windows (CR LF). Save file.
Open file with LTSpice. Schematic opens with no apparent issue and simulation runs at 20us/s. Close file.
Open asc file with Notepad++. Edit, Select all, Copy.
Paste into this post below.
Note that \ characters in TEXT -336 -528 Left 2 line have now become \\
Examine post after sending and make another post.

Version 4
SHEET 1 3608 920
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WIRE -1360 -2400 -1680 -2400
WIRE -1200 -2400 -1360 -2400
WIRE -1104 -2400 -1200 -2400
WIRE -736 -2400 -1104 -2400
WIRE -320 -2400 -736 -2400
WIRE 208 -2400 -320 -2400
WIRE 336 -2400 208 -2400
WIRE 576 -2400 336 -2400
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========== REMAINDER OF ARTICLE TRUNCATED ==========