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From: "Edward Rawde" <invalid@invalid.invalid>
Newsgroups: sci.electronics.design
Subject: Re: Current mirror version of the lowish distortion 1kHz sine wave osillator
Date: Thu, 23 Jan 2025 13:18:10 -0500
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"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vmso7m$1gtf6$1@dont-email.me...
> On 23/01/2025 10:56 am, Edward Rawde wrote:
>> "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vmpj6v$i521$1@dont-email.me...
>>> On 22/01/2025 12:32 pm, Bill Sloman wrote:
>>>> On 22/01/2025 3:58 am, Edward Rawde wrote:
>>>>> "Edward Rawde" <invalid@invalid.invalid> wrote in message news:vmogqg$23tl$1@nnrp.usenet.blueworldhosting.com...
>>>>>> "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vmninh$3t6oi$1@dont-email.me...
>>>>>>> On 21/01/2025 2:19 am, Bill Sloman wrote:
>>>>>>>> On 15/01/2025 11:33 pm, Bill Sloman wrote:
>>>
>>> <snip>
>>>
>>>> It is running on LTSpice 17.0 on Windows 7, and I do have to download 17.1, which I'm going to do right now.
>>>
>>> What you get if you are running Windows 7 is version 17.0.36.0, which may explain the difference. The sim runs just as fast on 
>>> the
>>> newly uploaded software. It's unlikely that John May has stuck to Window 7. and he has reported here that he is getting the same
>>> kind of speed.
>>>
>>> Don posted much the same observation earlier.
>>
>> I put LTSpice XVII(X64) (17.0.34.0) in the administrator account of an older core i5 2.8GHz (not SSD) running Windows 11 home 
>> 23H2.
>> I'll be upgrading it to Windows 10 pro when I get a chance.
>> I didn't install any suggested LTSpice updates.
>> U1 was out of position but this time I had to move it up and connect the -ve power rail.
>> Simulation speed varies between about 6ms/s and 15 ms/s.
>> Vout shows a single transient at startup which peaks at about 600mv pk and settles to a constant level of around 100mV pk in a 
>> few
>> hundred ms.
>> FFT of a sample of about 100ms near 10s with Blackman Harris window shows 1kHz a little below -20dB,
>> 2kHz -90dB (so at least 70 dB down on 1 kHz)
>> 3kHz -70dB
>> 4kHz -85dB
>> 5kHz  -75dB
>> There are no higher peaks or crud at higher frequencies.
>> The raw file didn't go above 1.1 GB
>>
>> Now move exactly the same circuit to LTSpice 24.1.0 on a core i7 SSD Windows 10 pro 22H2.
>> LTSpice component updates available today 22 Jan 2025 were also installed.
>> U1 now has to be moved down and the +ve rail has to be connected.
>> Note that after saving the file in 24.1.0 the version at the top of the file becomes 4.1
>> Take a sample of about 10us of Vout between 300-350us and do FFT with Blackman-Harris window.
>> This shows a peak of -43dB at 24MHz and the next highest peak -93dB at 400MHz.
>> Zoom to fit and watch progress. Reported speed is about 25us/s.
>> Leave simulation running and do some other work.
>> Come back after an hour and find it has peaked at 600mV pk after 86ms simulation time and is now falling.
>> Take a sample of a few cycles at 86ms and run FFT with Blackman-Harris window.
>> 1kHz -9dB
>> 2kHz -95dB
>> 3kHz -85dB
>> 4kHz -110dB
>> 24MHz -63dB
>> raw file has reached 40GB and simulation time is now 130ms. Level is 200mv pk and still falling
>> Level seems reasonably stable (100mv pk) at 220ms but take a sample and you can see it has parasitic HF crud in it.
>> raw file has now reached 74GB. Stop simulation.
>>
>> All signal amplitude levels given are pk. pk-pk would be twice.
>>
>> To avoid any doubt of what I'm simulating, it's below.
>
> And the problem with your version of the circuit is that C10 on the output of U4 was 3.3? rather than 3.3u, We've had that problem 
> before.

Aha for some reason I thought that your circuit didn't have any u symbols.
It's 3300n now.
In any case that's easy to fix. Just open the asc file in a real editor (Notepad++)
Under Encoding, Convert to ANSI and save the file.
I usually do this with any file obtained online but for some reason I thought that yours had no u symbols.
There's also an option in LTSpice under Tools, Settings (Control Panel in your case), Netlist Options convert u to u which I haven't 
tested yet.

>
> The LTC6655-1.25 at U1 is an an excellent voltage reference if it is loaded with at least 2.7uF. Technically speaking I should be 
> using the Greek symbol. Using 3300nF is safer, because not every LTSpice user takes advantage of the option to treat "u" as if was 
> the correct Greek alphabet look-alike.

I'll be doing ANSI conversion in Notepad++ every time now.

>
> Without enough output capacitance the LTSpice model for the LTC6655-1.25 behaves oddly. I screwed up early on and only used 1uF 
> and the part oscillated.
>
> In your version of the circuit it presents a slowly rising ramp starting at 0V which had crept up to 10mV after 2 seconds.
>
> This doesn't produce the behaviour I intended.
>
> There's also a problem with the BAS70L diode model - your version leaves off the .ENDS line at the end of the Spice directive. The 
> simulation appears to run fine without it, at 30msec/sec, but I'm still nervous about it.

Removing .ENDS from the BAS70L model doesn't make any difference with versions of LTSpice prior to 24.1.0
But if it's present when you try to simulate in 24.1.0 you'll get errors which make no sense and don't mention BAS70L.

Your circuit still includes the MMBF4391 model which doesn't have .ENDS so why should BAS70L care?
I converted BAS70L to a single line in the circuit below, with no difference in simulation that I can see.
I've also removed MMBF4391

So now let's simulate the corrected circuit (included below) in 24.1.0 with all updates and also in 17.0.34.0 with no updates at 
all.

In 24.1.0 the first thing we see is an 0.6V ramp shaped spike lasting about 2us. This appears to be just a startup transient of no 
consequence.
The next thing we see is what looks like 24MHz parasitic oscillation at a level of about 10mV pk
Zooming up shows a sinewave with some clipping between -8mV and +10mV.
Placing cursors on the trace confirms 24MHz.
Reported simulation speed doesn't go above 30us/s
Leave simulation running and copy file to another computer running LTSpice 17.0.34.0

U1 is displaced downwards so move it up and connect -ve rail.
Simulation now shows five or six settling transients lasting about 0.7s before the output settles at about 1.8V pk
Reported simulation speed varies but is mostly between 5 and 12 ms/s
Allow simulation to run to 10s. Take a sample of about 100ms near 10s and FFT with Blackman-Harris window.
1kHz 0dB
2kHz -62dB
3kHz -50dB
4kHz -60dB
5kHz -50dB
6kHz -63dB
7kHz -55dB
8kHz -70dB
9kHz -60dB
10kHz -75dB
Take a sample of a few cycles near 10s. Don't see anything at 24MHz.

Go back to 24.1.0 simulation.
It's at about 120ms near the end of the first transient which peaks at 5V.
Take a sample of a few cycles with amplitude near 2V pk
1kHz slightly above 0dB
2kHz -80dB
3kHz -78dB
4kHz -100dB
5kHz -88dB
6kHz -110dB
7kHz -95dB
8kHz -115dB
9kHz -98dB
10kHz -115dB
24MHz -62dB

Conclusion. The difference between the two simulations has nothing to do with C10 or .ENDS in BAS70L but I'd still like to know what 
it is.

The circuit below was last saved in 17.0.34.0. Check the position and connection of U1 before simulating.

Version 4
SHEET 1 3608 920
WIRE -1680 -2400 -1984 -2400
WIRE -1360 -2400 -1680 -2400
WIRE -1200 -2400 -1360 -2400
WIRE -1104 -2400 -1200 -2400
WIRE -736 -2400 -1104 -2400
WIRE -320 -2400 -736 -2400
WIRE 208 -2400 -320 -2400
WIRE 336 -2400 208 -2400
WIRE 576 -2400 336 -2400
WIRE -736 -2384 -736 -2400
WIRE 208 -2384 208 -2400
WIRE -320 -2368 -320 -2400
WIRE 3376 -2272 -1616 -2272
WIRE 880 -2192 -1776 -2192
WIRE -1360 -2160 -1360 -2400
WIRE -736 -2160 -736 -2320
WIRE -656 -2160 -736 -2160
WIRE -320 -2160 -320 -2304
WIRE -176 -2160 -320 -2160
WIRE 208 -2144 208 -2320
WIRE 336 -2144 208 -2144
WIRE -1200 -2112 -1200 -2400
WIRE -1680 -2096 -1680 -2400
WIRE -1360 -2048 -1360 -2080
WIRE -320 -2000 -320 -2160
WIRE -736 -1984 -736 -2160
WIRE -1776 -1968 -1776 -2192
WIRE 336 -1968 336 -2144
WIRE 576 -1968 576 -2400
WIRE -1360 -1920 -1360 -1968
WIRE -1200 -1920 -1200 -2032
WIRE 1952 -1920 1744 -1920
WIRE 2160 -1920 1952 -1920
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