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From: Stephen Fuld <sfuld@alumni.cmu.edu.invalid>
Newsgroups: comp.arch
Subject: Re: DRAM Chiplet for L3 cache?
Date: Mon, 27 Jan 2025 11:14:46 -0800
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On 1/27/2025 9:18 AM, Anton Ertl wrote:
> Stephen Fuld <sfuld@alumni.cmu.edu.invalid> writes:
>> This brings up the question of why, at least so far, no one is using a
>> DRAM chiplet (i.e. one made with a DRAM specialized technology), for the
>> L3 cache.  ISTM that the advantage of being able to put a much higher
>> capacity cache in the same physical size chiplet is substantial.
> 
> There used to be eDRAM used for an L4 cache ("Crystall Well") in some
> Intel Broadwell and Skylake variants, as well as eDRAM used as L3
> cache on Power8.  There is an insightfull article on Crystal Well (as
> well as a little bit about Power8):
> <https://old.chipsandcheese.com/2024/11/01/broadwells-edram-vcache-before-vcache-was-cool/>,
> which also provides an explanation why this technology is no longer
> used.

Thank you Anton.  You're right, that article is excellent.  I knew about 
the eDRAM used in some Power systems, but not Intel's use.  The article 
explains the issues very well.  It seems like one of those things that 
sounds good at first, but as you get into the details, the problems 
become more evident, and the paper illustrated that very well.


-- 
  - Stephen Fuld
(e-mail address disguised to prevent spam)