Path: ...!eternal-september.org!feeder3.eternal-september.org!news.eternal-september.org!eternal-september.org!.POSTED!not-for-mail
From: BGB <cr88192@gmail.com>
Newsgroups: comp.arch
Subject: Re: Cost of handling misaligned access
Date: Tue, 4 Feb 2025 14:49:14 -0600
Organization: A noiseless patient Spider
Lines: 68
Message-ID: <vntuga$20mq1$1@dont-email.me>
References: <5lNnP.1313925$2xE6.991023@fx18.iad>
 <2025Feb2.184458@mips.complang.tuwien.ac.at> <vnocer$q8bq$1@dont-email.me>
 <vnr7f2$1egqs$1@dont-email.me> <vnrb15$105p$1@gal.iecc.com>
 <112ffb344782247afc7b5e9e36c085d5@www.novabbs.org>
 <s1hoP.141118$qu83.118261@fx35.iad>
 <12d9d216c9a094ef963217baa35793e9@www.novabbs.org>
 <vQtoP.308267$zX7.230802@fx37.iad>
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8; format=flowed
Content-Transfer-Encoding: 8bit
Injection-Date: Tue, 04 Feb 2025 21:49:15 +0100 (CET)
Injection-Info: dont-email.me; posting-host="22115392b13e851cba501cc091e01343";
	logging-data="2120513"; mail-complaints-to="abuse@eternal-september.org";	posting-account="U2FsdGVkX18fquX7uwpSRs1VGpco7RIExUWBISq9eNM="
User-Agent: Mozilla Thunderbird
Cancel-Lock: sha1:Ciac2u/S67fPqQ+6x4Mi17VrxfY=
Content-Language: en-US
In-Reply-To: <vQtoP.308267$zX7.230802@fx37.iad>
Bytes: 3574

On 2/4/2025 1:25 PM, Scott Lurndal wrote:
> mitchalsup@aol.com (MitchAlsup1) writes:
>> On Tue, 4 Feb 2025 4:49:57 +0000, EricP wrote:
>>
>>> MitchAlsup1 wrote:
>>>>
>>>> Basically, VAX taught us why we did not want to do "all that" in
>>>> a single instruction; while Intel 432 taught us why we did not bit
>>>> aligned decoders (and a lot of other things).
>>>
>>> I case people are interested...
>>>
>>> [paywalled]
>>> The Instruction Decoding Unit for the VLSI 432 General Data Processor,
>>> 1981
>>> https://ieeexplore.ieee.org/abstract/document/1051633/
>>>
>>> The benchmarks in table 1(a) below tell it all:
>>> a 4 MHz 432 is 1/15 to 1/20 the speed (slower) than a 5 MHz VAX/780,
>>> 1/4 to 1/7 speed than a 8 MHz 68000 or 5 MHz 8086
>>>
>>> A Performance Evaluation of The Intel iAPX 432, 1982
>>> https://dl.acm.org/doi/pdf/10.1145/641542.641545
>>>
>>> And the reasons are covered here:
>>>
>>> Performance Effects of Architectural Complexity in the Intel 432, 1988
>>> https://www.princeton.edu/~rblee/ELE572Papers/Fall04Readings/I432.pdf
>>
>>From the link::
>> The 432’s procedure calls are quite costly. A typical procedure call
>> requires 16 read accesses to memory and 24 write accesses, and it
>> consumes 982 machine cycles. In terms of machine cycles, this makes
>> it about ten times as slow as a call on the MC68010 or VAX 11/780.
>>
>> almost 1000 cycles just to call a subroutine !!!
>>
>> Lots of thinigs teh architects got wrong in there.....
> 
> While true, it's easy to say in retrospect after forty+
> years of advancements in silicon design and technology.
> 
> Comparing to the CISC architectures of the 60s and 70s,
> it's not horrible.


Well, vs a modern RISC style ISA, say, caller side:
   MOV  R20, R10  //0c (SSC with following)
   MOV  R21, R11  //1c
   BSR  func     //2c (typically)
Cost: 3 cycles.

func:
   ADD SP, -32, SP      //2c (1 c penalty)
   MOV.Q  LR, (SP, 24)  //1c
   MOV.X  R18, (SP, 0)  //1c
   ...
   MOV.Q  (SP, 24), LR  //2c (1c penalty)
   MOV.X  (SP, 0), R18  //1c
   JMP    LR            //10c (*1)

*1: Insufficient delay since LR reload, so branch predictor fails to 
handle this case.

Cost: 16 cycles.

....