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Path: ...!news.mixmin.net!eternal-september.org!feeder3.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: john larkin <jl@650pot.com> Newsgroups: sci.electronics.design Subject: faster DDS clock Date: Wed, 18 Sep 2024 14:39:39 -0700 Organization: A noiseless patient Spider Lines: 8 Message-ID: <vphmejhqgb8br7j2u5dq7dus2schvi2rpu@4ax.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Injection-Date: Wed, 18 Sep 2024 23:39:01 +0200 (CEST) Injection-Info: dont-email.me; posting-host="378033aed3ff8e5a111ea52e9148454b"; logging-data="244455"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/YRDBZGnQ/gSlNNcfjWqJO" User-Agent: ForteAgent/8.00.32.1272 Cancel-Lock: sha1:I0duq6j94Cbes4H2K5SDptq6eb0= Bytes: 1243 Assume a DAC being driven with an n-bit sine waveform at some clock frequency, and then a lowpass filter and a comparator, generating a programmable frequency clock. Why not use both edges of the comparator output as our clock? That de-stresses everything by 2:1, which could well be a net win on jitter and such. Or gives twice the clock frequency with the same parts.