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From: john larkin <jl@650pot.com>
Newsgroups: sci.electronics.design
Subject: faster DDS clock
Date: Wed, 18 Sep 2024 14:39:39 -0700
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Assume a DAC being driven with an n-bit sine waveform at some clock
frequency, and then a lowpass filter and a comparator, generating a
programmable frequency clock.

Why not use both edges of the comparator output as our clock? That
de-stresses everything by 2:1, which could well be a net win on jitter
and such. Or gives twice the clock frequency with the same parts.