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Path: ...!weretis.net!feeder9.news.weretis.net!news.quux.org!eternal-september.org!feeder3.eternal-september.org!news.eternal-september.org!eternal-september.org!.POSTED!not-for-mail From: Lawrence D'Oliveiro <ldo@nz.invalid> Newsgroups: comp.arch Subject: Re: Why VAX Was the Ultimate CISC and Not RISC Date: Sun, 2 Mar 2025 00:16:06 -0000 (UTC) Organization: A noiseless patient Spider Lines: 11 Message-ID: <vq0805$etiq$1@dont-email.me> References: <vpufbv$4qc5$1@dont-email.me> <2025Mar1.125817@mips.complang.tuwien.ac.at> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Injection-Date: Sun, 02 Mar 2025 01:16:07 +0100 (CET) Injection-Info: dont-email.me; posting-host="4879a8900fe2dd21742e8795ad5f83f5"; logging-data="489050"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18MxvgDXzXD5HYnwPemePgw" User-Agent: Pan/0.162 (Pokrosvk) Cancel-Lock: sha1:B94UuqlQjl765DJOUesOeWVjjR8= Bytes: 1534 On Sat, 01 Mar 2025 11:58:17 GMT, Anton Ertl wrote: > Like other USA-based computer architects, Bell ignores ARM, which > outperformed the VAX without using caches and was much easier to design. While those ARM chips were legendary for their low power consumption (and low transistor count), those Archimedes machines were not exactly low- cost, as I recall. Without caches, did they have to use faster (and therefore more expensive) memory? Or did they fall back on the classic “wait states”?