Deutsch   English   Français   Italiano  
<vqh07g$26ac$1@dont-email.me>

View for Bookmarking (what is this?)
Look up another Usenet article

Path: ...!eternal-september.org!feeder3.eternal-september.org!news.eternal-september.org!eternal-september.org!.POSTED!not-for-mail
From: "Fred. Zwarts" <F.Zwarts@HetNet.nl>
Newsgroups: comp.theory
Subject: Re: DD correctly emulated by HHH --- Totally ignoring invalid
 rebuttals ---PSR---
Date: Sat, 8 Mar 2025 09:47:44 +0100
Organization: A noiseless patient Spider
Lines: 56
Message-ID: <vqh07g$26ac$1@dont-email.me>
References: <vq5qqc$1j128$2@dont-email.me> <vq78ni$1u8bl$3@dont-email.me>
 <5e786c32c2dcc88be50183203781dcb6a5d8d046@i2pn2.org>
 <vq866t$23nt0$1@dont-email.me>
 <2002d599ebdfb7cd5a023881ab2faca9801b219d@i2pn2.org>
 <vq8l3d$29b9l$1@dont-email.me>
 <4426787ad065bfd0939e10b937f3b8b2798d0578@i2pn2.org>
 <vq8mam$29b9l$5@dont-email.me>
 <920b573567d204a5c792425b09097d79ee098fa5@i2pn2.org>
 <vq9lvn$2ei4j$3@dont-email.me>
 <4453bc0c1141c540852ea2223a7fedefc93f564c@i2pn2.org>
 <vqadoh$2ivg7$2@dont-email.me> <vqae74$2ivcn$1@dont-email.me>
 <vqag6q$2jief$1@dont-email.me> <vqagb7$2ivcn$3@dont-email.me>
 <vqakhi$2jief$3@dont-email.me> <vqalvr$2ivcn$5@dont-email.me>
 <vqaq2s$2lgq7$2@dont-email.me> <vqasm4$2lue4$1@dont-email.me>
 <vqb43k$2mueq$1@dont-email.me> <vqb4ub$2lue4$3@dont-email.me>
 <vqb683$2mueq$2@dont-email.me> <vqbp05$2td95$1@dont-email.me>
 <vqcvlu$34c3r$3@dont-email.me> <vqecht$3epcf$1@dont-email.me>
 <vqf2lh$3j68u$5@dont-email.me> <vqf6mm$3j47v$4@dont-email.me>
 <vqg7ng$3qol2$3@dont-email.me>
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8; format=flowed
Content-Transfer-Encoding: 7bit
Injection-Date: Sat, 08 Mar 2025 09:47:45 +0100 (CET)
Injection-Info: dont-email.me; posting-host="111ebc5957824e612f76d2436b1c509b";
	logging-data="72012"; mail-complaints-to="abuse@eternal-september.org";	posting-account="U2FsdGVkX18KgAyRUQNJWgSWPoZEBGX9"
User-Agent: Mozilla Thunderbird
Cancel-Lock: sha1:KJU8iu0at422bqoleHzM7BfBpdM=
In-Reply-To: <vqg7ng$3qol2$3@dont-email.me>
Content-Language: nl, en-GB
Bytes: 4211

Op 08.mrt.2025 om 02:49 schreef olcott:
> On 3/7/2025 10:25 AM, Fred. Zwarts wrote:
>> Op 07.mrt.2025 om 16:17 schreef olcott:
>>> On 3/7/2025 2:59 AM, Fred. Zwarts wrote:
>>>> Op 06.mrt.2025 om 21:13 schreef olcott:
>>>>> On 3/6/2025 3:13 AM, Fred. Zwarts wrote:
>>>>>> Op 06.mrt.2025 om 04:53 schreef olcott:
>>>>>>> On 3/5/2025 9:31 PM, dbush wrote:
>>>>>>>> On 3/5/2025 10:17 PM, olcott wrote:
>>>>>>>>> On 3/5/2025 7:10 PM, dbush wrote:
>>>>>>>>>>
>>>>>>>>>> In other words, you know that what you're working on has 
>>>>>>>>>> nothing to do with the halting problem, but you don't care.
>>>>>>>>>
>>>>>>>>> In other words I WILL NOT TOLERATE ANY BULLSHIT DEFLECTION.
>>>>>>>>> You have proven that you know these things pretty well SO QUIT 
>>>>>>>>> THE SHIT!
>>>>>>>>>
>>>>>>>>
>>>>>>>> You want people to accept that HHH(DD) does in fact report that 
>>>>>>>> changing the code of HHH to an unconditional simulator and 
>>>>>>>> running HHH(DD) will not halt.
>>>>>>>>
>>>>>>>
>>>>>>> DD correctly emulated by HHH cannot possibly
>>>>>>> reach its own "ret" instruction and terminate normally.
>>>>>>
>>>>>> Yes, we agree that HHH fails to reach the 'ret' instruction, 
>>>>>
>>>>> Despicably dishonest attempt at the straw-man deception.
>>>>>
>>>>
>>>> No rebuttal. So, we agree that HHH fails to reach the 'ret' 
>>>> instruction. 
>>>
>>> Not at all. Trying to get away with changing the subject
>>> WILL NOT BE TOLERATED.
>>>
>> If you do not agree that HHH fails to reach the 'ret' instruction 
>> (that world-class simulators do reach, just as the direct execution 
>> does), show how it reaches the 'ret' instruction.
> 
> *set X*
> When-so-ever any input to any simulating termination
> analyzer calls the simulator that is simulating itself
> 
> *result of set X*
> this input cannot possibly reach its own final state
> and terminate normally because it remains stuck in
> recursive emulation.
> 

So, we agree that any simulator that tries to simulate *itself* cannot 
possibly reach the end of its simulation.
Why would we want to use such an analyser that reports that it fails to 
complete the simulation?