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From: Robert Finch <robfi680@gmail.com>
Newsgroups: comp.arch
Subject: Re: MSI interrupts
Date: Mon, 17 Mar 2025 17:33:50 -0400
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On 2025-03-17 11:53 a.m., Scott Lurndal wrote:
> Here's a copy of a slide I did a decade ago for ARM64 (GICv3) interrupts,
> not much has changed since.
> 
>                Interrupt Gates
> 
>   There are a number of gates that must be open to pass an interrupt
>   from the source to the destination Core
> 
>     ­ Device Interrupt Enable Register (e.g. A NIC receive interrupt enable)
>     ­ MSI-X Vector Enable (mask bit in each MSI-X vector control register)
>     ­ MSI-X PCI-Express Capability Enable (enable bit and function mask in MSI-X
>       Capability message control field)
>     ­ The PCI CMD register must have bus mastering enabled
>     ­ GICv3 Distributor/Redistributor/LPI Properties per-interrupt enable bit
>     ­ GICv3 Group Enable in distributor (GICD_CTLR)
>     ­ GICv3 Group Enable in Target core (ICC_IGRPEN{01}_EL1)
>     ­ Priority Mask register and current running priority on target core
>     ­ ARM64 core interrupt signal Mask (PSTATE.A/I/F)
> 
> Interrupt group, in this context, defines the security state of
> the interrupt (group 0: secure, group 1: non-secure) and is a
> configuration bit associated with each interrupt.

Yes, there is a lot that has to happen for an interrupt to occur. Q+ 
gets to skip the step about enabling bus mastering as it uses the slave 
response bus.

I have got something like the following so far:

	set device interrupt enable, MSI message in device
	enable the vector in the interrupt table
	globally enable interrupts for the interrupt controller
	setup the interrupt affinities in the interrupt contoller
	set the per vector interrupt enable
	set the priorty threshold register in the IC
	set the priority level in the CPU core
	enable interrupts in the CPU