Path: ...!eternal-september.org!feeder3.eternal-september.org!news.eternal-september.org!eternal-september.org!.POSTED!not-for-mail
From: Robert Finch <robfi680@gmail.com>
Newsgroups: comp.arch
Subject: Re: MSI interrupts
Date: Wed, 19 Mar 2025 13:27:46 -0400
Organization: A noiseless patient Spider
Lines: 36
Message-ID: <vreuqm$1b741$1@dont-email.me>
References: <vqto79$335c6$1@dont-email.me>
 <53b8227eba214e0340cad309241af7b5@www.novabbs.org>
 <3pXAP.584096$FVcd.26370@fx10.iad>
 <795b541375e3e0f53e2c76a55ffe3f20@www.novabbs.org>
 <vNZAP.37553$D_V4.18229@fx39.iad>
 <aceeec2839b8824d52f0cbe709af51e1@www.novabbs.org>
 <eM_AP.81303$8rz3.7843@fx37.iad> <vr2nj9$2goqe$1@dont-email.me>
 <f2cb846242dbfcef1efa59b92763a965@www.novabbs.org>
 <vr4ovm$9fl5$1@dont-email.me>
 <1681197d3c1af131d6b8cae884f7c9ca@www.novabbs.org>
 <vr7g76$2jnqm$1@dont-email.me> <8BVBP.816276$eNx6.247046@fx14.iad>
 <20250317161132.00004dd9@yahoo.com> <1WZBP.558392$SZca.243157@fx13.iad>
 <ef12021b16a514c71a5cab2f0efa60c7@www.novabbs.org>
 <jwvh63puk31.fsf-monnier+comp.arch@gnu.org>
 <f6cf175a3fbc6893f5bea834bbf3b7f2@www.novabbs.org>
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8; format=flowed
Content-Transfer-Encoding: 8bit
Injection-Date: Wed, 19 Mar 2025 18:27:50 +0100 (CET)
Injection-Info: dont-email.me; posting-host="d20416905c284720f56106b72be0c6a6";
	logging-data="1416321"; mail-complaints-to="abuse@eternal-september.org";	posting-account="U2FsdGVkX18Pw1LQQH5BMoUP84AOJL/aei2EG4+kR+Q="
User-Agent: Mozilla Thunderbird
Cancel-Lock: sha1:Q3gNw6njTW04kCJtT7ndTMzQnRM=
In-Reply-To: <f6cf175a3fbc6893f5bea834bbf3b7f2@www.novabbs.org>
Content-Language: en-US
Bytes: 3065

On 2025-03-19 12:00 p.m., MitchAlsup1 wrote:
> On Wed, 19 Mar 2025 15:20:20 +0000, Stefan Monnier wrote:
> 
>> MitchAlsup1 [2025-03-17 21:49:18] wrote:
>>> On Mon, 17 Mar 2025 18:33:09 +0000, EricP wrote:
>>>> Method 1 is simplest, it injects the interrupt request at Retire
>>>> as that's where the state of everything is synchronized.
>> [...]
>>> Lowest interrupt Latency
>>> Highest waste of power (i.e., work)
>>>
>>>> Method 2 pipelines the switch by injecting the interrupt request at
>>>> Fetch.
>> [...]
>>> Interrupt latency is dependent on executing instructions,
>>> Lowest waste of power
>>
>> What do existing CPUs do?
> 
> Lean in the direction of method 2 will fallback position of method 1
> if anything goes wrong.
> 
>> Method 2 looks insanely messy, so I'd assume method 1 is the standard
>> approach, right?
> 
> It is "not that bad" on the large scale of things.
> 
Undaunted he tries to implement the method 2 approach using an IRQ 
victim queue for IRQs that should not be processed at retire. It is not 
too bad to code, but I dunno if it works yet. Just a switch at fetch 
time to select from the victim queue first, otherwise pop the normal IRQ 
queue. The queue is small, assuming that IRQs are not disabled for great 
lengths of time.
>>
>>         Stefan