Deutsch   English   Français   Italiano  
<vrntrs$1ab2q$1@dont-email.me>

View for Bookmarking (what is this?)
Look up another Usenet article

Path: news.eternal-september.org!eternal-september.org!.POSTED!not-for-mail
From: Robert Finch <robfi680@gmail.com>
Newsgroups: comp.arch
Subject: Re: Split instruction and immediate stream
Date: Sat, 22 Mar 2025 23:06:34 -0400
Organization: A noiseless patient Spider
Lines: 42
Message-ID: <vrntrs$1ab2q$1@dont-email.me>
References: <vqhjpv$65am$1@dont-email.me> <vqiikd$c35o$1@dont-email.me>
 <fmnzP.432863$2zn8.70525@fx15.iad>
 <16462d5aa26345e4e015f240b30bba02@www.novabbs.org>
 <vrm4vt$3o4ta$1@dont-email.me> <vrmjhv$5hkp$1@dont-email.me>
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8; format=flowed
Content-Transfer-Encoding: 7bit
Injection-Date: Sun, 23 Mar 2025 04:06:37 +0100 (CET)
Injection-Info: dont-email.me; posting-host="aa5e56903d1e415e420aab3152ccfb55";
	logging-data="1387610"; mail-complaints-to="abuse@eternal-september.org";	posting-account="U2FsdGVkX184Jn9pzd3udahR/8h9s331KRuQruKnw74="
User-Agent: Mozilla Thunderbird
Cancel-Lock: sha1:5mIBgUP6rsnSEPxfsVbCUq4q4/8=
Content-Language: en-US
In-Reply-To: <vrmjhv$5hkp$1@dont-email.me>

On 2025-03-22 11:04 a.m., Thomas Koenig wrote:
> Marcus <m.delete@this.bitsnbites.eu> schrieb:
> 
>> Then we have the page-crossing issue. Is it better to force the
>> compiler/assembler to align such instructions so that they never cross
>> page boundaries?
> 
> Power 10 chose to do so; actually, larger instructions cannot
> cross a (likely) Cache line size there.  According to the Power
> ISA Version 3.1, section 1.6:
> 
> "Prefixed instructions do not cross 64-byte instruction address
> boundaries. When a prefixed instruction crosses a 64-byte boundary,
> the system alignment error handler is invoked."

In the latest test project, the LB650 similar to a PowerPC, large 
constants are encoded at the end of the cache line. So, there is a 
similar issue of code running into the constant area.

I have the assembler moving the code that overlaps to the next cache line.

It is confusing to look at listing files, as there are constants output 
inline with the code. Makes it look like the code should not work. How 
does it know where to go for the next instruction? Is the question that 
comes to mind.

For now, the hardware decoder takes the cheezy approach of marking 
instructions fetched in the constant area as invalid. The constant area 
gets fetched and loaded into the pipeline, but as NOPs.

It is quite a trick getting the assembler to place constants at the end 
of the cache line and generate references to the constants. It is 
interesting because I have *constants* being relocated by the assembler 
/ linker. Normally there would not be a relocation associated with a 
constant. A relocation reference to the constant is spit out by the 
assembler, and the linker updates the index to the constant in the code.

It does not quite work yet. Constants are placed and code is moved, but 
the linked program does not have the correct references yet.

Experimental, but looking like things will work.