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From: Robert Finch <robfi680@gmail.com>
Newsgroups: comp.arch
Subject: Re: Split instruction and immediate stream
Date: Sun, 23 Mar 2025 19:13:25 -0400
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On 2025-03-23 9:44 a.m., Thomas Koenig wrote:
> Robert Finch <robfi680@gmail.com> schrieb:
> 
>> In the latest test project, the LB650 similar to a PowerPC, large
>> constants are encoded at the end of the cache line. So, there is a
>> similar issue of code running into the constant area.
> 
> What is your motivation for this?

This was more of a two day experiment. Wanted to see if code density 
could be improved.

I have gone back to Q+ which maybe has better code density.
Got a better result after putting more work into the assembler.
For my serial I/O routines:

PowerPC: 1624 bytes (compiled with vbcc)
Q+: 1456 bytes (arpl compiler)

I am guessing most of the gain is from function prolog / epilog where Q+ 
has enter / leave instructions. There is still a couple of issues in the 
arpl compiler, it outputs more instructions than it needs to. Those 
24-bit instructions work well.

> 
> If you have an instruction including constant(s) which no longer
> fits your cache line (say, 8 bytes left and 12 bytes needed)
> it does not matter where you put the constants and where you
> put the instructions - it will not fit, and you have to start
> a new cache line.

Yes.
> 
> I am not seeing an advantage over what Power 10 does, which is
> just to add a NOP at the end if things don't fit on a cacheline.

NOP ramps in my parlance. I use them to handle crossing page boundaries.