Path: ...!eternal-september.org!feeder3.eternal-september.org!news.eternal-september.org!eternal-september.org!.POSTED!not-for-mail
From: Robert Finch <robfi680@gmail.com>
Newsgroups: comp.arch
Subject: Re: Constant Stack Canaries
Date: Fri, 4 Apr 2025 23:45:51 -0400
Organization: A noiseless patient Spider
Lines: 33
Message-ID: <vsq91i$18k1q$1@dont-email.me>
References: <vsbcnl$1d4m5$1@dont-email.me> <vsc058$20pih$1@dont-email.me>
 <4cf60b5fd8b785feb07a67a823cc349d@www.novabbs.org>
 <vseeen$l4ig$1@dont-email.me> <vseiq9$qndj$1@dont-email.me>
 <e05e9d429f71944bbfe74c3f54b79a03@www.novabbs.org>
 <vseojq$112f7$1@dont-email.me>
 <62b5c4a25d917c5bab64a815189de826@www.novabbs.org>
 <vshf6a$3smcv$1@dont-email.me>
 <21397906a7a77c2d43191fdaab98a3c9@www.novabbs.org>
 <jwv4iz75l6k.fsf-monnier+comp.arch@gnu.org> <vsidun$sput$2@dont-email.me>
 <jwvtt752vg1.fsf-monnier+comp.arch@gnu.org> <vsmg8a$16gr3$1@dont-email.me>
 <vsnksc$2fkk9$1@dont-email.me>
 <6a77fabdb64f59e4497ef3353d747441@www.novabbs.org>
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8; format=flowed
Content-Transfer-Encoding: 7bit
Injection-Date: Sat, 05 Apr 2025 05:45:55 +0200 (CEST)
Injection-Info: dont-email.me; posting-host="f2578ad01345e6a95ad44c9886455064";
	logging-data="1331258"; mail-complaints-to="abuse@eternal-september.org";	posting-account="U2FsdGVkX19n2HqKUUFa0BtaxQUWiHveeu8I1XiNuW0="
User-Agent: Mozilla Thunderbird
Cancel-Lock: sha1:JDUJUmrKueV3KlTwTECBxGufSUo=
In-Reply-To: <6a77fabdb64f59e4497ef3353d747441@www.novabbs.org>
Content-Language: en-US
Bytes: 2990

On 2025-04-04 5:13 p.m., MitchAlsup1 wrote:
> On Fri, 4 Apr 2025 3:49:31 +0000, Robert Finch wrote:
> 
>> On 2025-04-03 1:22 p.m., BGB wrote:
> -------------------
>>>
>>> Or, to allow for NOMMU operation, or reduce costs by not having context
>>> switches result in as large of numbers of TLB misses.
>>>
>>> Also makes the kernel simpler as it doesn't need to deal with each
>>> process having its own address space.
>>
>> Have you seen the MPRV bit in RISCV? Allows memory ops to execute using
>> the previous mode / address space. The bit just has to be set, then do
>> the memory op, then reset the bit. Makes it easy to access data using
>> the process address space.
> 
> Let us postulate you are running in RISC-V HyperVisor on core[j]
> and you want to write into GuestOS VAS and into application VAS
> more or less simultaneously.
> 
Would not writing to the GuestOs VAS and the application VAS be the 
result of separate system calls? Or does the hypervisor take over for 
the GuestOS?

> Seems to me like you need a MPRV to be more than a single bit
> so it could index which layer of the SW stack's VAS it needs
> to touch.

So, there is a need to be able to go back two or three levels? I suppose 
it could also be done by manipulating the stack, although adding an 
extra bit may be easier. How often does it happen?