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From: Thomas Koenig <tkoenig@netcologne.de>
Newsgroups: comp.arch
Subject: Re: fractional PCs
Date: Wed, 30 Apr 2025 18:09:30 -0000 (UTC)
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Robert Finch <robfi680@gmail.com> schrieb:

> When I first heard about micro-ops I envisioned them as being smaller 
> than the instructions in the ISA because of the term "micro". For 
> instance 16 or even 12-bits. I was having a heck of time trying to 
> implement with 16-bit micro-ops. Then I clued in, why not just make them 
> bigger? They're not really micro-ops, it is more like mega-ops.

AMD uses 64-bit micro-ops, see the link I posted recently (and
again, below).  It is actually a RISC-like ISA, which makes sense,
because you don't want to spend a lot of time decoding micro-ops.
They have 64 bit micro-op length, and most fields they could have
in any instruction has its unique place.

https://bughunters.google.com/blog/5424842357473280/zen-and-the-art-of-microcode-hacking

>
> Current micro-op structure:
>
> typedef struct packed {
> 	logic v;		// valid bit
> 	logic [2:0] count;	// number of micro-ops for instruction
> 	logic [2:0] num;	// the micro-op of the instruction
> 	logic [1:0] xRs2;	// extended register selection bits
> 	logic [1:0] xRs1;
> 	logic [1:0] xRd;
> 	logic [3:0] xop4;
> 	instruction_t ins;	// The instruction
> } micro_op_t;

Hmm... I don't know what your ISA looks like, but having the
original instruction looks strange.  Why not take a page from
AMD's book?  It looks like a reasonable philosophy, and obviously it
works for them, or they would have done something different by now.