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From: Bill Sloman <bill.sloman@ieee.org>
Newsgroups: sci.electronics.design,comp.dsp
Subject: Re: DDS question: why sine lookup?
Date: Sat, 10 May 2025 18:53:07 +1000
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On 10/05/2025 5:53 am, john larkin wrote:
> On Fri, 9 May 2025 04:48:33 -0000 (UTC), piglet
> <erichpwagner@hotmail.com> wrote:
> 
>> Phil Hobbs <pcdhSpamMeSenseless@electrooptical.net> wrote:
>>> john larkin <jl@glen--canyon.com> wrote:
>>>> On Thu, 8 May 2025 22:28:40 -0000 (UTC), Phil Hobbs
>>>> <pcdhSpamMeSenseless@electrooptical.net> wrote:
>>>>
>>>>> john larkin <jl@glen--canyon.com> wrote:
>>>>>> On Thu, 8 May 2025 16:24:29 -0400, Phil Hobbs
>>>>>> <pcdhSpamMeSenseless@electrooptical.net> wrote:
>>>>>>
>>>>>>> On 2025-05-08 14:58, john larkin wrote:
>>>>>>>> On Thu, 8 May 2025 14:20:21 -0400, Phil Hobbs
>>>>>>>> <pcdhSpamMeSenseless@electrooptical.net> wrote:
>>>>>>>>
>>>>>>>>> On 2025-05-07 22:21, john larkin wrote:
>>>>>>>>>> On Wed, 7 May 2025 20:27:58 -0400, bitrex <user@example.net> wrote:
>>>>>>>>>>
>>>>>>>>>>> On 5/7/2025 4:01 PM, john larkin wrote:
>>>>>>>>>>>> On Wed, 7 May 2025 20:32:41 +0100, Martin Brown
>>>>>>>>>>>> <'''newspam'''@nonad.co.uk> wrote:
>>>>>>>>>>>>
>>>>>>>>>>>>> On 06/05/2025 16:48, john larkin wrote:

<snip>

>>> The difference between adjacent magic increments isn’t that large, at least
>>> at lowish frequencies. It might well be possible to dork the clock to get
>>> to the nearest one.
> 
> FPGAs have PLLs too, low GHz range, which can be programmed to be K
> times our 40 MHz XO, for modest values of K.  Then one can divide
> down, not always by a freely chosen divider... often with a
> first-stage divider of small N... some sort of ring counter maybe.
> 
> Lots of nasty number theory.

The catch with a VCO inside an FPGA is going to be the ripple on the 
supply voltages inside the FPGA.

Its output will have appreciable jitter. The charm of the Phil Hobbs 
VCXO is that it will be a low jitter source - probably at the 
pico-second level

>> Yes. Surely these are lowish frequencies as early on in the discussion JL
>> said all this was to simulate rotating machines?
> 
> Yes. The existing product has a user-programmable clock up to 15 MHz,
> all the expensive ADI DDS chip would do.

You couldn't do that with Phil Hobbs VCXO as your VCO. A 150MHz VXCO 
would limit you about 15hHz, which is probably all that your customers need.
Giving then a lot more than they need always makes the salesmen happy, 
but it doesn't do anything for the customer.

> With the maximum size
> waveform table (65K points) the output waveform rate is 229 Hz. The
> thing is due for redesign, and we'd like to go faster on the clock, 20
> MHz at least, preferably more.
> 
> https://highlandtechnology.com/Product/V375
> 
> Arbs are plentiful and cheap, but this one was designed specifically
> to simulate geared rotating machines.

So optimise it for the frequencies they want, and chop the performance 
in areas they won't use.

-- 
Bill Sloman, Sydney