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From: Bill Sloman <bill.sloman@ieee.org>
Newsgroups: sci.electronics.design,comp.dsp
Subject: Re: DDS question: why sine lookup?
Date: Sun, 11 May 2025 16:55:55 +1000
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On 11/05/2025 9:50 am, Dave Platt wrote:
> In article <ad7v1kttjfhjulnameem9ta8gjst5cpa45@4ax.com>,
> john larkin  <jl@glen--canyon.com> wrote:
> 
>> Looks like the best way is logic in the FPGA doing classic sine DDS,
>> maybe 6 or 8 output pins driving an R-2R network, a 3 or 5-pole
>> Chebyshev LC filter, and an LVDS receiver as the comparator.
> 
> Be wary of that approach.
> 
> I tried something like it (sans comparator), while using a simple FPGA
> to generate a (modulated) 10.7 MHz IF signal for an FM-stereo test
> generator.  The results were ungood.
> 
> The output waveform had some pretty horrible glitches, at the times of
> the transitions between values.  There's enough variation in delay in
> the signal paths inside the FPGA to create a significant (in
> picoseconds and nanoseconds) delay between the transition times of the
> R2R bits.  If you're trying to go from (for example) 0x7F to 0x81,
> your MSB is going to be transitioning high when most of your LSBs are
> transitioning low.  There's very likely to be a brief moment of time
> when the effective value is 0xFF (if the MSB transitions first) or
> 0x00 (if it transitions last), or some random and unpredictable and
> ever-changing mix of bits.  The resulting spikes are narrow, but can
> have a pretty fierce amplitude to them.
One approach that might help, but isn't going to be all that cheap, 
would be to latch the digital information coming out of the FPGA into 
something like an ECLinPS latch which has very fast internal logic and 
rather less variation in propagation delay between the clock edge going 
into the ECLinPS latch and the output edges of the data outputs.

The other advantage is that ECL is current steering logic, so the latch 
rails are a lot clean than the rails inside the FPGA and the nominally 
unchanged edges aren't going to move as much.

-- 
Bill sloman. Sydney