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From: Al Kossow <aek@bitsavers.org>
Newsgroups: comp.arch
Subject: Re: Is Parallel Programming Hard, And, If So, What Can You Do About
 It?
Date: Sun, 11 May 2025 07:47:53 -0700
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On 5/11/25 6:59 AM, Scott Lurndal wrote:
> mitchalsup@aol.com (MitchAlsup1) writes:
>> Summary:: Devices need just as much cache coherence as cores--maybe
>> more.
> 
> Does a uart need cache coherence?   How about a SPI or MMC controller?
> 

I had wondered about SOCs like the RPi Pico
With the narrow memory interfaces,
are cores starved for memory bandwidth?