Path: ...!weretis.net!feeder8.news.weretis.net!eternal-september.org!feeder3.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: anton@mips.complang.tuwien.ac.at (Anton Ertl) Newsgroups: comp.arch Subject: Re: Instruction counts (was: Decrement And Branch) Date: Fri, 16 Aug 2024 07:43:31 GMT Organization: Institut fuer Computersprachen, Technische Universitaet Wien Lines: 36 Message-ID: <2024Aug16.094331@mips.complang.tuwien.ac.at> References: <2024Aug14.111001@mips.complang.tuwien.ac.at> <2024Aug15.123928@mips.complang.tuwien.ac.at> <1f9360728a7b19bcbf3660565adfa2f5@www.novabbs.org> <2024Aug16.072330@mips.complang.tuwien.ac.at> Injection-Date: Fri, 16 Aug 2024 10:03:25 +0200 (CEST) Injection-Info: dont-email.me; posting-host="f685176504da3451b219cd11a88d6053"; logging-data="1444468"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+CkvVkLrY3Ek9i3ZiEbX3+" Cancel-Lock: sha1:UJPTJqrr8abbdUS6PquVuj00KOI= X-newsreader: xrn 10.11 Bytes: 2867 Lawrence D'Oliveiro writes: >On Fri, 16 Aug 2024 05:23:30 GMT, Anton Ertl wrote: > >> ... instruction count was not >> among the criteria that John Mashey identified as discerning between >> RISC and non-RISC (not surprising given non-RISCs like PDP-11). > >Why is that particular criterion, of all of them, in the name, then? It is not. It's not Reduced InstructionS Computer, but "Reduced Instruction Set Computer", and Mashey argued convincingly that this should be read as "reduced-instruction set computer", not as "reduced instruction-set computer". If it was "reduced instruction-set computer", then the RISCs should have kept the VAX shift instruction, which shifted in either direction, depending on the sign of the shift count. Instead, RISCs generally split this instruction into a shift-left and shift-right instruction, increasing the instruction count. >At one point I thought it should be “IRSC”, for “Increased Register Set >Computer” ... This is one commonality of RISCs, but does not discern between RISCs like the original IBM 801 (16 registers) and ARM A32 on one hand, and S/360, VAX and AMD64 on the other hand (and especially not AMD64 with APX). In any case, number of registers certainly is one of the criteria that John Mashey uses, but he uses a number of criteria, and these work well for classifying architectures that he did not classify in his original postings <2024Jan12.145502@mips.complang.tuwien.ac.at>. - anton -- 'Anyone trying for "industrial quality" ISA should avoid undefined behavior.' Mitch Alsup,