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Failed to connect to MySQL: (1203) User howardkn already has more than 'max_user_connections' active connectionsPath: ...!eternal-september.org!feeder3.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: john larkin Newsgroups: sci.electronics.design Subject: Re: faster DDS clock Date: Sun, 22 Sep 2024 13:32:11 -0700 Organization: A noiseless patient Spider Lines: 113 Message-ID: <87v0fj9ppucbefmql1nvf504rjg7uronh3@4ax.com> References: <3r7nejdbihkhugevrmvvkvos85roknqrv5@4ax.com> <08qtej59j66s3segectheulp0nbje108pu@4ax.com> <54tuejh1gdvq6i2tist29h0ikmmo55ks3u@4ax.com> <18tuejd5robbpp4sfq0k17kgn68sr38k76@4ax.com> MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit Injection-Date: Sun, 22 Sep 2024 22:32:14 +0200 (CEST) Injection-Info: dont-email.me; posting-host="0e575bd28907a0d4d7c2e2db73b8b931"; logging-data="2471146"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/Tkr214A2C7PJiosdtrLu2" User-Agent: ForteAgent/8.00.32.1272 Cancel-Lock: sha1:BSuthn33IsohsQyAb/Acg4r9fmg= Bytes: 5670 On Sun, 22 Sep 2024 18:37:54 +0200, Lasse Langwadt wrote: >On 9/22/24 03:40, john larkin wrote: >> On Sat, 21 Sep 2024 18:37:26 -0700, john larkin wrote: >> >>> On Sun, 22 Sep 2024 03:11:53 +0200, Lasse Langwadt >>> wrote: >>> >>>> On 9/21/24 17:42, john larkin wrote: >>>>> On Fri, 20 Sep 2024 00:30:28 +0200, Lasse Langwadt >>>>> wrote: >>>>> >>>>>> On 9/19/24 05:57, john larkin wrote: >>>>>>> On Thu, 19 Sep 2024 03:28:09 -0000 (UTC), Phil Hobbs >>>>>>> wrote: >>>>>>> >>>>>>>> john larkin wrote: >>>>>>>>> On Wed, 18 Sep 2024 21:56:59 -0000 (UTC), Phil Hobbs >>>>>>>>> wrote: >>>>>>>>> >>>>>>>>>> john larkin wrote: >>>>>>>>>>> Assume a DAC being driven with an n-bit sine waveform at some clock >>>>>>>>>>> frequency, and then a lowpass filter and a comparator, generating a >>>>>>>>>>> programmable frequency clock. >>>>>>>>>>> >>>>>>>>>>> Why not use both edges of the comparator output as our clock? That >>>>>>>>>>> de-stresses everything by 2:1, which could well be a net win on jitter >>>>>>>>>>> and such. Or gives twice the clock frequency with the same parts. >>>>>>>>>>> >>>>>>>>>>> >>>>>>>>>> >>>>>>>>>> The usual trouble is that you have to get the other edge from somewhere. An >>>>>>>>>> xor gate and an RC is typical. >>>>>>>>>> >>>>>>>>>> Any asymmetry in the square wave turns into subharmonic jitter. >>>>>>>>>> >>>>>>>>>> A 2:1 PLL would probably get my vote. >>>>>>>> >>>>>>>>> >>>>>>>>> I'm trying to make things cheaper and simpler. I need a clock that's >>>>>>>>> programmable up to maybe 20 or 25 MHz, and it would be nice to use >>>>>>>>> some relatively cheap dual DACs. >>>>>>>> >>>>>>>> Understood. A Joergesque solution would be to use a discrete FET as part >>>>>>>> of the RC + XOR, and dork the ON resistance to square up the duty cycle. >>>>>>>> (He’d probably use a CD4007 DIY gate package to do a few at once. Maybe >>>>>>>> it’s possible to use a TinyLogic inverter with VDD open.) >>>>>>>> >>>>>>>> Cheers >>>>>>>> >>>>>>>> Phil Hobbs >>>>>>> >>>>>>> An LVDS line receiver would make a pretty good comparator, after the >>>>>>> filter. >>>>>>> >>>>>>> If I have enough balls (no pun intended) I can use an LVDS input of my >>>>>>> FPGA. One could even servo that to exactly 50%. >>>>>>> >>>>>>> I don't know if this FPGA could internally clock on both edges. >>>>>>> >>>>>>> But I can get a TI DAC908 for under $5, so may just clock that fast, >>>>>>> brute force at 100 MHz or so. That would make 20 MHz with a dinky >>>>>>> filter. >>>>>>> >>>>>> >>>>>> this will give you 3x10bit@140MHZ DACs for about the same price >>>>>> https://www.lcsc.com/product-detail/Digital-to-Analog-Converters-DAC_Analog-Devices-ADV7123KSTZ140-RL_C172724.html >>>>>> >>>>>> or 3x8bit@330MHz >>>>>> https://www.lcsc.com/product-detail/Digital-to-Analog-Converters-DAC_Analog-Devices-ADV7125JSTZ330_C662165.html >>>>>> >>>>>> if you opt for the Chinese clone, less than half for 3x10bit@240MHz >>>>>> https://www.lcsc.com/product-detail/Digital-to-Analog-Converters-DAC_HTCSEMI-HT7123ARQZ_C2886392.html >>>>>> >>>>>> >>>>>> >>>>>> >>>>>> >>>>> >>>>> It occurrs to me that the use for a 3-channel fast 10-bit DAC is to >>>>> drive a color CRT monitor, which I expect nobody makes any more. >>>>> >>>> >>>> It's for VGA (that's why it has sync and blank input) >>>> While VGA is old I doubt it is going anywhere soon, it still widely >>>> used, go buy a server and it has VGA >>>> >>> >>> Seems silly to take digital data, convert it to analog, ship it six >>> feet, and convert it back to digital. >> >> And why do we have those firehoses of HDMI connectors and cables? Why >> not use Ethernet or USB out to a monitor? > >HDMI is ~10-20 times the bandwidth of regular ethernet Maybe some gamers need multi-gigabit bandwidth. I can watch a movie that arrives at my house over a cable modem and CAT5 or WiFi to my computers. So a CAT5 from the computer to a monitor should be OK. > >there are plenty of monitors that can use USB-C > That's sensible. The HDMI connectors and cables are klunky. We really only need ethernet, USB-c, and one unified wireless/wifi network.