Path: ...!weretis.net!feeder9.news.weretis.net!reader5.news.weretis.net!news.solani.org!.POSTED!not-for-mail From: Jan Panteltje Newsgroups: sci.electronics.design Subject: Re: faster DDS clock Date: Fri, 20 Sep 2024 05:11:38 GMT Message-ID: References: <3r7nejdbihkhugevrmvvkvos85roknqrv5@4ax.com> MIME-Version: 1.0 Content-Type: text/plain; ISO-8859-15 Content-Transfer-Encoding: 8bit Injection-Date: Fri, 20 Sep 2024 05:11:38 -0000 (UTC) Injection-Info: solani.org; logging-data="436481"; mail-complaints-to="abuse@news.solani.org" User-Agent: NewsFleX-1.5.7.5 (Linux-5.15.32-v7l+) Cancel-Lock: sha1:9vsXXA9vYNG8FQrWiZgmi05Dl48= X-Newsreader-location: NewsFleX-1.5.7.5 (c) 'LIGHTSPEED' off line news reader for the Linux platform NewsFleX homepage: http://www.panteltje.nl/panteltje/newsflex/ and ftp download ftp://sunsite.unc.edu/pub/linux/system/news/readers/ X-User-ID: eJwFwYEBACAEBMCViH8Zp8T+I3QHo7LCCToGky/Xu3WqN8z2NYmkpioo292kEVdIZ69sHF2cQMWLrHG1DzMrFFc= Bytes: 4174 Lines: 67 On a sunny day (Fri, 20 Sep 2024 00:30:28 +0200) it happened Lasse Langwadt wrote in : >On 9/19/24 05:57, john larkin wrote: >> On Thu, 19 Sep 2024 03:28:09 -0000 (UTC), Phil Hobbs >> wrote: >> >>> john larkin wrote: >>>> On Wed, 18 Sep 2024 21:56:59 -0000 (UTC), Phil Hobbs >>>> wrote: >>>> >>>>> john larkin wrote: >>>>>> Assume a DAC being driven with an n-bit sine waveform at some clock >>>>>> frequency, and then a lowpass filter and a comparator, generating a >>>>>> programmable frequency clock. >>>>>> >>>>>> Why not use both edges of the comparator output as our clock? That >>>>>> de-stresses everything by 2:1, which could well be a net win on jitter >>>>>> and such. Or gives twice the clock frequency with the same parts. >>>>>> >>>>>> >>>>> >>>>> The usual trouble is that you have to get the other edge from somewhere. An >>>>> xor gate and an RC is typical. >>>>> >>>>> Any asymmetry in the square wave turns into subharmonic jitter. >>>>> >>>>> A 2:1 PLL would probably get my vote. >>> >>>> >>>> I'm trying to make things cheaper and simpler. I need a clock that's >>>> programmable up to maybe 20 or 25 MHz, and it would be nice to use >>>> some relatively cheap dual DACs. >>> >>> Understood. A Joergesque solution would be to use a discrete FET as part >>> of the RC + XOR, and dork the ON resistance to square up the duty cycle. >>> (He’d probably use a CD4007 DIY gate package to do a few at once. Maybe >>> it’s possible to use a TinyLogic inverter with VDD open.) >>> >>> Cheers >>> >>> Phil Hobbs >> >> An LVDS line receiver would make a pretty good comparator, after the >> filter. >> >> If I have enough balls (no pun intended) I can use an LVDS input of my >> FPGA. One could even servo that to exactly 50%. >> >> I don't know if this FPGA could internally clock on both edges. >> >> But I can get a TI DAC908 for under $5, so may just clock that fast, >> brute force at 100 MHz or so. That would make 20 MHz with a dinky >> filter. >> > >this will give you 3x10bit@140MHZ DACs for about the same price >https://www.lcsc.com/product-detail/Digital-to-Analog-Converters-DAC_Analog-Devices-ADV7123KSTZ140-RL_C172724.html > >or 3x8bit@330MHz >https://www.lcsc.com/product-detail/Digital-to-Analog-Converters-DAC_Analog-Devices-ADV7125JSTZ330_C662165.html > >if you opt for the Chinese clone, less than half for 3x10bit@240MHz >https://www.lcsc.com/product-detail/Digital-to-Analog-Converters-DAC_HTCSEMI-HT7123ARQZ_C2886392.html Last time I used a R2R DAC on my FPGA .. was only 8 bit though.. video https://panteltje.nl/pub/FPGA_board_with_25MHz_VCXO_locked_to_rubidium_10MHz_reference_IMG_3724.GIF bottom board top right, all the resistors...