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From: jseigh <jseigh_es00@xemaps.com>
Newsgroups: comp.arch
Subject: Re: Arm ldaxr / stxr loop question
Date: Mon, 11 Nov 2024 09:56:44 -0500
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On 11/11/24 08:59, Scott Lurndal wrote:

> 
> There are fully atomic instructions,  the load/store exclusives are
> generally there for backward compatability with armv7; the full set
> of atomics (SWP, CAS, Atomic Arithmetic Ops, etc) arrived with
> ARMv8.1.
> 

They added the atomics for scalability allegedly.  ARM never
stated what the actual issue was.  I suspect they couldn't
guarantee a memory lock size small enough to eliminate
destructive interference.  Like cache line size instead
of word size.

Joe Seigh