Path: ...!weretis.net!feeder9.news.weretis.net!news.nk.ca!rocksolid2!i2pn2.org!.POSTED!not-for-mail From: mitchalsup@aol.com (MitchAlsup1) Newsgroups: comp.arch Subject: Re: Interview with Power's chief designer Date: Sun, 29 Dec 2024 01:58:52 +0000 Organization: Rocksolid Light Message-ID: References: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Injection-Info: i2pn2.org; logging-data="946756"; mail-complaints-to="usenet@i2pn2.org"; posting-account="o5SwNDfMfYu6Mv4wwLiW6e/jbA93UAdzFodw5PEa6eU"; User-Agent: Rocksolid Light X-Rslight-Site: $2y$10$MR6PSuUInO/ZNgzQFED43OqjBudaKOpWBYeKtAmnxnbVQI5WnK3SS X-Rslight-Posting-User: cb29269328a20fe5719ed6a1c397e21f651bda71 X-Spam-Checker-Version: SpamAssassin 4.0.0 Bytes: 2048 Lines: 25 On Fri, 27 Dec 2024 13:29:22 +0000, Thomas Koenig wrote: > Not sure how many of you read Chips and Cheese, but in case you're > interested: Here is an inteview with IBM Power's chief designer, > Bill Starke: > > https://old.chipsandcheese.com/2024/12/26/ibm-power-whats-next/ > > There is a lot of talk on OMI (he really doesn't like DDR, and gives > reasons, especially the amount of memory and reliability), plus some > detail on POWER11, which apparently will be a microarchitectural > evolution, but no new ISA parts, and the philosophy behind the > chiplet design they are about to do for the next generation after > that. He makes a compelling point that DDR is using too many pins and still does not provide the desired BW available for that number pf pins. And that a SEREDS interface to DRAMs provide easier to achieve signaling and larger memories at the same time--similar to what CXL:memory is attempting. > Apparently, nobody knows what its name will be, but it might > be something like "Power 11 plus one". Let me take a guess:: {I have to state that I have heard and read nothing}