Path: ...!news-out.netnews.com!postmaster.netnews.com!us8.netnews.com!not-for-mail X-Trace: DXC=:iQW8`a@NMUB5LNaTKYZ7SU5[F2hIijD_7J470dMQQ7[J4R`5ADBYnR78WECPL4LUW\lfPTGbeKk[[0;UX[nH\RXUh:ZAVm]2iT1NI1l8fb?f^XlnNGcjcaFT X-Complaints-To: support@frugalusenet.com Date: Mon, 10 Feb 2025 22:59:23 -0500 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: SPLD output current protection Newsgroups: sci.electronics.design References: <67aa8442$0$1895507$882e4bbb@reader.netnews.com> <27hlqjlujra8hgmfvhed0h0bpnd9jmkb81@4ax.com> Content-Language: en-US From: bitrex In-Reply-To: <27hlqjlujra8hgmfvhed0h0bpnd9jmkb81@4ax.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Lines: 33 Message-ID: <67aacb1a$7$2873015$882e4bbb@reader.netnews.com> NNTP-Posting-Host: 127.0.0.1 X-Trace: 1739246362 reader.netnews.com 2873015 127.0.0.1:37103 Bytes: 2587 On 2/10/2025 10:41 PM, john larkin wrote: > On Mon, 10 Feb 2025 17:57:06 -0500, bitrex wrote: > >> I have an SPLD with about 8 terminals exposed to the user I'd like to >> protect against over current. They're very low-speed outputs (10s of Hz >> at most), don't really want to spend a bunch for a chip like the L6374 >> as an intermediary, or the board space for a bunch of transistors to >> discrete limit... >> >> The SPLD has a max per-chip-side Vdd input current of 45 mA at 85 C TJ >> and 22 mA at 110 TJ, and can sink 86 mA to ground per side, 41 at 110 TJ. >> >> The outputs are configured as push-pull or open drain, depending on the >> firmware/application, either way they can source or sink 40mA in >> isolation. But no more than two outputs per side at a time will be in a >> state such that they can sink/source current either way. >> >> The uP I'm using has a very nice 10 bit differential ADC (9 bits if used >> in bipolar mode) I'm thinking about just rigging it to two 4051s to >> "scan" a current sense in each output line to implement the overcurrent, >> can set different thresholds based on whether it's configured push-pull >> or OD, but what might conservative limits be? And what rate to scan? >> >> The SPLD is acting as a simple power supervisor and has a PWR GOOD line >> to bring up the uP. In turn it gets a clock from the uP, I can set up >> the SPLD to set all those outputs hi-z if it ever loses the clock (i.e. >> uP hangs) as an extra layer of protection.. > > What's an SPLD? > > If it ain't a FPGA or a CPLD it's an SPLD. I think.