Path: ...!weretis.net!feeder9.news.weretis.net!news.nk.ca!rocksolid2!i2pn2.org!.POSTED!not-for-mail From: mitchalsup@aol.com (MitchAlsup1) Newsgroups: comp.arch Subject: Re: Split instruction and immediate stream Date: Sat, 8 Mar 2025 23:56:14 +0000 Organization: Rocksolid Light Message-ID: References: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Injection-Info: i2pn2.org; logging-data="3506734"; mail-complaints-to="usenet@i2pn2.org"; posting-account="o5SwNDfMfYu6Mv4wwLiW6e/jbA93UAdzFodw5PEa6eU"; User-Agent: Rocksolid Light X-Rslight-Posting-User: cb29269328a20fe5719ed6a1c397e21f651bda71 X-Spam-Checker-Version: SpamAssassin 4.0.0 X-Rslight-Site: $2y$10$SwZ/gYfyizFHZZnqcgNWsuUq1fgjdhg9mbRyzy1ilk5W7K606kOvi Bytes: 2855 Lines: 48 On Sat, 8 Mar 2025 17:53:34 +0000, MitchAlsup1 wrote: > On Sat, 8 Mar 2025 14:21:51 +0000, Thomas Koenig wrote: > >> There was a recent post to the gcc mailing list which showed >> interesting concept of dealing with large constants in an ISA: >> Splitting a the instruction and constant stream. It can be found >> at https://github.com/michaeljclark/glyph/ , and is named "glyph". > > I knew a guy with that name at AMD--he did microcode--and did it well. > >> I think the problem the author is trying to solve is better addressed by >> My 66000 (and I would absolutely _hate_ to write an assembler for it). >> Still, I thought it worth mentioning. > > I took a quick look, and it seems that > a) too few registers > b) too many OpCode bits > although it does look easy to parse. The length decode is wasteful of bits. There are 4 sizes of instructions 16, 32, 54, 128 denoted by the first halfword having (respectively) 00, 01, 10, 11. But successive halfwords contain 2-bits that simply waste entropy and could have been used for "other good stuff". 16-bit instructions get a 5-bit opcode, and the entire 32 instruction space is already fully populated. 32-bit instructions get a 10-bit OpCode space. At this point I should note that my entire OpCode instruction space has only 62 instructions. 64-bit instructions get a 20-bit OpCode space. Nobody is going to need 1M individual instructions. So, a bit of rearrangement would provide for a healthy OpCode space and more bits for registers, and possibly a 96-bit instruction in- stead of a 128-bit instruction. So, we are still missing:: a) a memory order model b) a translation model c) atomic instructions d) external linkage {code and data} e) thread support using his {ip, bp) construct f) system call model g) debug model h) timers and counters i) floating point ...