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From: mitchalsup@aol.com (MitchAlsup1)
Newsgroups: comp.arch
Subject: Re: Scan chains
Date: Thu, 8 May 2025 01:04:42 +0000
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On Wed, 7 May 2025 19:03:31 +0000, Stefan Monnier wrote:

>>> What's the approximate cost of those scan chains.  I.e. if we were to
>>> take an existing working design and replace all the "flip-flop with
>>> scan-chain" with "plain flip-flops", how much smaller would the
>>> resulting chip be, how much faster could it run, and how much less power
>>> could it consume?
>> Given a 16-gate delay design with 5 gates of "flop-jitter-skew"
>> the scan path adds about ½ a gate of delay (2%-ish).
>
> Almost lost in the noise.  Thanks.

Such a big gain in debugging, such a small penalty for use ...

>
>         Stefan